ver. 0.04 Revision A 14/02/99
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 DEBUG- Finally fixed load file command bug. Phew!
        Added more commands (see readnow.txt)
        Added multiple breakpoints for each CPU.
        Fixed a problem with breakpoints. If target
        for a delayed jump it would stop on delay op.
        Irritating more than anything else.
 MEM  - Rewrote mem command to directly support differing
        memory areas (i.e. ROM,RAM and REGS).
 CPU  - Added Cache memory Proably never be needed.
 SCU  - Added all three DMA levels. Full direct and 
        indirect support (I hope!)
 SCU  - Finally fixed up Timer0 and Timer1 operation.
        Umm insufficient testing on my part.
 CPU  - Finally added Dual CPU support. Most likely 
        wont do anything yet. Added FRT input capture 
        for CPU communication.
 CDROM- Added two basic commands for the interface. Get
        hardware info and get status. Returns NODISC 
        condition in the status area. Added periodic 
        response.

ver. 0.03 Revision B 17/11/98
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 Bug fix release.

 SCU  - Fixed Timer0 bug causing it to call its interrupt
        on every cycle. Didnt notice it until I profiled.
 CPU  - Added slight speed increase (about 20%) lost
        when using Z command.
 CDROM- Added simple memory write to location 25890008
        (Writes 0xBE1) Not sure what it exactly does
        Command reg??

ver. 0.03 Revision A 14/11/98
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 DEBUG- Fixed stupid C error in set byte command
 DEBUG- Tidyed disassembler,now display absolute
        mem addresses where possible. 
 DEBUG- Added new command (I) call interrupt.
 DEBUG- Added simple output log file. "log.txt"
 DEBUG- Fixed load file command bug?? Sort of!!!
 CPU  - Added Interrupt support.
 CPU  - Fixed bug in MOVLS4 opcode call. Prevented certain
        values being written to the stack.
 CDROM- Added CD ID string ???? Prevents a loop in BIOS
 SCU  - Added interrupt registering, Master SH2 interrupt masking
        Timer0 and Timer1 operation.
 SMPC - Tied operation to VBlank, Added partial INTBACK,
        RESET ENABLE,RESET DISABLE commands.
 VDP2 - Added HBlank, and Vblank interrupt generation

ver. 0.02 Revision A 15/9/98
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 SMPC - Added some SMPC commands MSHON,SSHON/OFF SETSMEM
 CPU  - Fixed a (possible??) bug in the opcodes BRAF + BSR ??
        caused BIOS to go into strange endless loop.
 CPU  - CPU Reset now reads PC reset vector and SP from BIOS area
 CPU  - Added preliminary support for cache controller and int controller
        i.e. has memory allocated for regs.
 CPU  - Simple cyclecounting setup. Always takes minimum cycles length.
 DEBUG- Added new debugger commands (l) load file to mem (k) set breakpoint.
 DEBUG- Changed reg RF to show SP in debugger. Think of the possibilities :)
 CPU  - BIOS now essential!!!!!

ver. 0.01 Revision A 10/9/98
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 First public release. 

 CPU  - Finished off opcodes.
        Entire CPU routines will be rewritten when needed (i.e. NOT now)
 CPU  - Added delay slot support
 DEBUG- Added new debugger commands (q) reset Master CPU (b) move byte to mem
        (z) execute code until keypressed.
 SMPC - Added preliminary support for SMPC (i.e. write 0 to status flag)
        to prevent endless CPU loops.
 DEBUG- Changed debugger screen to nice dissasmbler with regs displayed
        instead of single line opcodes.

ver. 0.001a ??/??/98
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
 DEBUG- Finished off Dissasmbler for now. rewrite not yet needed.
 DEBUG- Added basic debugger commands.
 CPU  - setup support for opcodes
 CDROM- Wrote external program to read Saturn header info.

ver. 0.0000000000000000000000000001a ??/??/98
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 DEBUG- Started on dissasmbler procedures.
 GENERAL-Started collecting info on Saturn!!!!

What's next.

These are my top priorities at the moment.

CPU      - Big speed up required. No doubt have to do that rewrite which has 
           been on the cards for a long time :)
CPU      - Add DMAC controller!
SMPC     - Add all commands. Maybe even look into trying to get a pad up and workin'
CDROM    - Try and finish my documentation of the cd interface. Try and work out
           how to read raw data from a cdrom drive (including subheaders etc) 
RAM CART - Could add this as it would take me 30 secs. Cant see the point
           at moment as no program can get far enough for the RAM CART access without
           CD ROM interface.
VDP      - Try and start on grafix emulation.

TyRaNiD ELA97JAF@sheffield.ac.uk
