Known bugs and restrictions of Emu42 V1.32
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- the following Lewis I/O bits aren't emulated
  DSPTEST (0x302) [VDIG LID CLTM1 CLTM0]
  DSPCTL  (0x303) [SDAT BIN]
  LPE     (0x309) [EVRAM RST]
  RAMTST  (0x30B) [PLEV XTRA DDP DPC]
  INPORT  (0x30C) [RX SREQ ST1 ST0]
  LEDOUT  (0x30D) [UREG EPD DRL]
- the following Sacajawea I/O bits aren't emulated
  DTEST   (0x302) [VDIG LID CLTM1 CLTM0]
  CTRL    (0x303) [SDAT VLBIS BIN]
  LPE     (0x309) [EVRAM RST]
  RAMTST  (0x30B) [PLEV XTRA DDP DPC]
- the following Bert I/O bits aren't emulated
  System Test Nibble (0x02) [PLEV VDIG DDP DPC]
  Mode Register      (0x03)
- Register and Display/Timer MMU configuration isn't separated

08/26/25 (c) by Christoph Gieelink
