[MAME]

Taito SJ system

Memory map
----------

MAIN CPU:

Address          Dir Data     Name       Description
---------------- --- -------- ---------- -----------------------
000xxxxxxxxxxxxx R   xxxxxxxx ROM5       program ROM
001xxxxxxxxxxxxx R   xxxxxxxx ROM6       program ROM
010xxxxxxxxxxxxx R   xxxxxxxx ROM7       program ROM
011xxxxxxxxxxxxx R   xxxxxxxx ROM8/ROM9  program ROM (banked)
10000xxxxxxxxxxx R/W xxxxxxxx SRAMRQ     work RAM
10001----------0 R   xxxxxxxx 8800       68705 data read
10001----------1 R   -------x 68ACCEPT   the 68705 has read data from the Z80
10001----------1 R   ------x- 68READY    the 68705 has written data for the Z80
10001----------0   W xxxxxxxx            68705 data write [3]
10001----------1   W -------- ZINTRQ     trigger IRQ on 68705 [3]
1001xxxxxxxxxxxx R/W xxxxxxxx CDR1-2     character generator RAM
101xxxxxxxxxxxxx R/W xxxxxxxx CDR3-6     character generator RAM
1100xxxxxxxxxxxx R/W xxxxxxxx CHARQ      tilemap RAM [4]
11010000xxxxxxxx R/W xxxxxxxx SCRRQ      tilemap column scroll
11010001xxxxxxxx R/W xxxxxxxx OBJRQ      sprites RAM [1]
11010010-xxxxxx0   W -------x VCRRQ      palette chip (93419)
11010010-xxxxxx1   W xxxxxxxx VCRRQ      palette chip (93419)
11010011--------   W ---xxxxx PRY        priority control [2]
11010100----0000 R   xxxxxxxx H0-H7      sprite 0..7 collided
11010100----0001 R   xxxxxxxx H8-H15     sprite 8..15 collided
11010100----0010 R   xxxxxxxx H16-H23    sprite 16..23 collided
11010100----0011 R   -------x OB1        sprite/tilemap 1 collision
11010100----0011 R   ------x- OB2        sprite/tilemap 2 collision
11010100----0011 R   -----x-- OB3        sprite/tilemap 3 collision
11010100----0011 R   ----x--- S12        tilemap 1/tilemap 2 collision
11010100----0011 R   ---x---- S13        tilemap 1/tilemap 3 collision
11010100----0011 R   --x----- S23        tilemap 2/tilemap 3 collision
11010100----0011 R   00------ S23        always 0
11010100----01-- R   xxxxxxxx EXRHR      read contents of graphics ROMs (address selected by d509-d50a)
11010100----1000 R   11xxxxxx IN0        digital inputs
11010100----1001 R   11xxxxxx IN1        digital inputs
11010100----1010 R   xxxxxxxx DP0        dip switch A
11010100----1011 R   --xxxxxx IN3        come from a PAL (ROM6 @ 14)
11010100----1011 R   xx------ IN3        digital inputs
11010100----1100 R   xxxxxxxx IN4        digital inputs
11010100----1101 R   ----xxxx IN5        digital inputs
11010100----1101 R   xxxx---- IN5        from AY-3-8910 #2 port A (status from sound CPU)
11010100----111x R/W xxxxxxxx READIN     AY-3-8910 #0
11010101----0000   W xxxxxxxx SPH1       tilemap 1 H scroll
11010101----0001   W xxxxxxxx SPV1       tilemap 1 V scroll
11010101----0010   W xxxxxxxx SPH2       tilemap 2 H scroll
11010101----0011   W xxxxxxxx SPV2       tilemap 2 V scroll
11010101----0100   W xxxxxxxx SPH3       tilemap 3 H scroll
11010101----0101   W xxxxxxxx SPV3       tilemap 3 V scroll
11010101----0110   W -----xxx MD1        tilemap 1 color code
11010101----0110   W ----x--- CCH1       tilemap 1 char bank
11010101----0110   W -xxx---- MD2        tilemap 2 color code
11010101----0110   W x------- CCH2       tilemap 2 char bank
11010101----0111   W -----xxx MD3        tilemap 3 color code
11010101----0111   W ----x--- CCH3       tilemap 3 char bank
11010101----0111   W --xx---- MD0        sprite color bank
11010101----0111   W xx------ n.c.
11010101----1000   W -------- HTCLR      clear hardware collision detection registers
11010101----1001   W xxxxxxxx EXROM1     low 8 bits of address to read from graphics ROMs
11010101----1010   W xxxxxxxx EXROM2     high 8 bits of address to read from graphics ROMs
11010101----1011   W xxxxxxxx EPORT1     command to sound CPU
11010101----1100   W -------x EPORT2     single bit signal to audio CPU (not used?)
11010101----1101   W -------- TIME RESET wathcdog reset
11010101----1110   W -------x COIN LOCK  coin lockout
11010101----1110   W ------x- SOUND STOP mute sound
11010101----1110   W -xxxxx-- n.c.
11010101----1110   W x------- BANK SEL   program ROM bank select
11010101----1111   W ---xxxxx EXPORT     to a PAL (ROM6 @ 14)
11010110--------   W -------x HINV       horizontal screen flip
11010110--------   W ------x- VINV       vertical screen flip
11010110--------   W -----x-- OBJEX      sprite bank select [1]
11010110--------   W ----x--- n.c.
11010110--------   W ---x---- SN1OFF     tilemap 1 enable
11010110--------   W --x----- SN2OFF     tilemap 2 enable
11010110--------   W -x------ SN3OFF     tilemap 3 enable
11010110--------   W x------- OBJOFF     sprites enable
11010111--------              n.c.
111xxxxxxxxxxxxx R   xxxxxxxx ROM10      program ROM


[1] There are 256 bytes of sprite RAM, but only 128 can be accessed by the
    video hardware at a time. OBJEX selects the high or low bank. The CPU can
    access all the memory linearly. This feature doesn't seem to be ever used
    although bioatack and spaceskr do initialise the second bank.

[2] Priority is controlled by a 256x4 PROM.
    Bits 0-3 of PRY go to A4-A7 of the PROM, bit 4 selectes D0-D1 or D2-D3.
    A0-A3 of the PROM is fed with a mask of the inactive planes in the order
    OBJ-SCN1-SCN2-SCN3. The 2-bit code which comes out from the PROM selects
    the plane to display.

[3] A jumper selects whether writing to 8800 should also automatically trigger
    the interrupt, or it should be explicitly triggered by a write to 8801.


[4] The first page of tilemap RAM c000-c3ff is used by bioatack during sprite
    collision detection. It is also initialised by wwestern and wwester1
    although they don't appear to use it.

SOUND CPU:

Address          Dir Data     Name      Description
---------------- --- -------- --------- -----------------------
0000xxxxxxxxxxxx R   xxxxxxxx ROM1      program ROM
0001xxxxxxxxxxxx R   xxxxxxxx ROM2      program ROM
0010xxxxxxxxxxxx R   xxxxxxxx ROM3      program ROM
0011xxxxxxxxxxxx R   xxxxxxxx ROM4      program ROM
010000xxxxxxxxxx R/W xxxxxxxx           work RAM
01001--------00x R/W xxxxxxxx CS5       AY-3-8910 #1
01001--------01x R/W xxxxxxxx CS5       AY-3-8910 #2
01001--------1-x R/W xxxxxxxx CS5       AY-3-8910 #3
01010---------00 R   xxxxxxxx RD5000    read command from main CPU
01010---------00   W -------- WR5000    clear bit 7 of command from main CPU (not used?)
01010---------01 R   ----x--- RD5001    command pending from main CPU (not used?)
01010---------01 R   -----x-- RD5001    single bit from main CPU (not used?)
01010---------01 R   ------11 RD5001    always 1
01010---------01   W -------- WR5001    clear single bit from main CPU (not used?)
01010---------10              n.c.
01010---------11              n.c.
111xxxxxxxxxxxxx R   xxxxxxxx           space for diagnostics ROM? not shown in the schematics



8910 #0
port A: DSW B
port B: DSW C

8910 #1
port A: digital sound out
port B: digital sound volume?

8910 #2:
port A: bits 4-7 IN54-IN57 read by main CPU at d40d
port B: n.c.

8910 #3:
port A: bits 0-1 control RC filter on this chip's output
port B: bit 0 NMI enable

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