[01/07/2000]

Taito -  Wardners Forest (1987)  Designed by Toaplan
----------------------------------------------------

Toaplan board number  : TP-009
Taito game number     : B25

Main CPU              : Z80B
Sound CPU             : Z80
Microcontroller       : TMS320C10  (Disguised as a Toaplan MCU)
Sound Chip            : YM3812
Crystal               : 24Mhz   (Bootleg board has a 14Mhz crystal)
Display Controller    : HD6845
Various other Toaplan address/data ASICS


Notes:
    The original games use a TMS320C10 DSP microcontroller but the chip isnt
    marked as such. The chip has a Toaplan label, and has the following
    markings actually under the label on the chip.

    Wardner:                           Sky Shark:
    D70012U                            D70012U
    GXC-02                             GXC-02
    MCU (Delta) 71900                  MCU 71400


    Flying Shark / Sky Shark have the same code as Wardner.

    The TMS320C10 code is internal to the chip and cannot be read.
    These DSP ROMS contained here are from bootleg boards which use standard
    TMS320C10 chips (with no internal code - all code is in external ROM)

    With the TMS320C10 DSP being a word based controller, the ROM code
    is split into two banks of nibble BPROMS. (82S137 and 82S131 chips)



Listing of ROM sets around with good ROMS. There is a PYROS set with a
bad ROM, and a Japanese bootleg set which turns out to contain a minor
hack of the world WARDNER CPU ROM, and uses the three Japanese title/text
graphic ROMs ???

(WARDNER)   Wardners Forest   Japanese copyright (English title screen logo)
(PYROS)     Pyros             USA copyright
(WARDNERJ)  Wardners Forest   Japanese copyright and title screen logo
(WARDNERB)  Wardners Forest   Bootleg Japanese copyright and title screen logo


ROM     PYROS set               WARDNER set             WARDNERJ set
size    FileNames   ZIP-CRC     FileNames   ZIP-CRC     FileNames    ZIP-CRC

65536   B25-01.ROM  42ec01fb    WARDNER.01  <-- same    WARDNERJ.01  <-- same
65536   B25-02.ROM  6c0130b7    WARDNER.02  <-- same    WARDNERJ.02  <-- same
65536   B25-03.ROM  b923db99    WARDNER.03  <-- same    WARDNERJ.03  <-- same
65536   B25-04.ROM  8059573c    WARDNER.04  <-- same    WARDNERJ.04  <-- same
16384   B25-33.ROM  9a55fcb9    WARDNER.05  79792c86    B25-05.BIN   be36a53e
16384   B25-34.ROM  02505dad    WARDNER.06  0ed848da    B25-06.BIN   3bfeb6ae
16384   B25-35.ROM  fec6f0c0    WARDNER.07  1392b60d    B25-07.BIN   50e329e0
32768   B25-08.ROM  883ccaa3    WARDNER.07  <-- same    WARDNERJ.08  <-- same
32768   B25-09.ROM  585411b7    WARDNER.09  <-- same    WARDNERJ.09  <-- same
32768   B25-10.ROM  b9a61e81    WARDNER.10  <-- same    WARDNERJ.10  <-- same
32768   B25-11.ROM  d6ebd510    WARDNER.11  <-- same    WARDNERJ.11  <-- same
32768   B25-12.ROM  15d08848    WARDNER.12  <-- same    WARDNERJ.12  <-- same
32768   B25-13.ROM  be21db2b    WARDNER.13  <-- same    WARDNERJ.13  <-- same
32768   B25-14.ROM  5a2aef4f    WARDNER.14  <-- same    WARDNERJ.14  <-- same
32768   B25-15.ROM  cdd2d408    WARDNER.15  <-- same    WARDNERJ.15  <-- same
32768   B25-16.ROM  e5202ff8    WARDNER.16  <-- same    WARDNERJ.16  <-- same
32768   B25-29.ROM  b568294d    WARDNER.17  c5dd56fd    B25-17.BIN   4164dca9
65536   B25-18.ROM  9aab8ee2    WARDNER.18  <-- same    WARDNERJ.18  <-- same
65536   B25-19.ROM  95b68813    WARDNER.19  <-- same    WARDNERJ.19  <-- same
32768   B25-30.ROM  5056c799    WARDNER.20  347f411b    B25-20.BIN   1113ad38
The following PROMS are from a bootleg Wardner board.
1024    82S137.3D   70b537b9
1024    82S137.1D   cc5b3f53
1024    82S137.1E   47351d55
1024    82S137.3E   6edb2de8
512     82S131.3A   712bad47
512     82S131.3B   9dfffaff
512     82S131.2A   ac843ca6
512     82S131.1A   50452ff8
256     82S129.B19  24e7d62f
256     82S129.B18  a50cef09
32      82S123.B21  f72482db
32      82S123.C6   bc88cced
32      82S123.F1   4fb5df2a

The bootleg Japanese set (originally called WARDNERJ) with the hacked world
Wardner CPU ROM   (WARDNERJ.17 - ZIP CRC is  c06804ec)


ROM legends:
----------------------------------------------

B25-01.ROM     \
B25-02.ROM      \ Sprite GFX ROMs
B25-03.ROM      /
B25-04.ROM     /
B25-33.ROM     \
B25-34.ROM      > Text and Title screen Layer GFX ROMs
B25-35.ROM     /
B25-08.ROM     \
B25-09.ROM      \ Back-ground layer GFX ROMs
B25-10.ROM      /
B25-11.ROM     /
B25-12.ROM     \
B25-13.ROM      \ Fore-ground layer GFX ROMs
B25-14.ROM      /
B25-15.ROM     /
B25-16.ROM     Sound Z80 CPU code ROM
B25-29.ROM     Main  Z80 CPU code ROM
B25-18.ROM     \
B25-19.ROM      > Main Z80 CPU GFX layout ROMs
B25-30.ROM     /

82s137.1-d     bits 15-12    \
82s137.1-e     bits 11-08     \ TMS320C10 code from address $000-$3ff  (words)
82s137.3-d     bits 07-04     /
82s137.3-e     bits 03-00    /

82s131.3-b     bits 15-12    \
82s131.3-a     bits 11-08     \ TMS320C10 code from address $400-$5ff  (words)
82s131.2-a     bits 07-04     /
82s131.1-a     bits 03-00    /

82S129.B19     \ Sprite priority control ?
82S129.B18     /
82S123.B21     Sprite control ?
82S123.C6      Sprite attribute (flip/position) ?
82S123.F1      Tile to Sprite priority ?

-


[MAME]

Z80:(0)  Main CPU
0000-6fff Main ROM
7000-7fff Main RAM
8000-ffff Level and scenery ROMS. This is banked with the following
8000-8fff Sprite RAM
a000-adff Pallette RAM
ae00-afff Spare unused, but tested Pallette RAM
c000-c7ff Sound RAM - shared with C000-C7FF in Z80(1) RAM

in:
50		DSW A
52		DSW B
54		Player 1 controls
56		Player 2 controls
58		VBlank (bit 7) and coin-in/start inputs
60		LSB data from char display layer
61		MSB data from char display layer
62		LSB data from BG   display layer
63		MSB data from BG   display layer
64		LSB data from FG   display layer
65		MSB data from FG   display layer

out:
00		6845 CRTC offset register
02		6845 CRTC register data
10		char scroll LSB   < Y >
11		char scroll MSB   < Y >
12		char scroll LSB     X
13		char scroll MSB     X
14		char LSB RAM offset     20h * 40h  (0-07ff) and (4000-47ff) ???
15		char MSB RAM offset
20		BG   scroll LSB   < Y >
21		BG   scroll MSB   < Y >
22		BG   scroll LSB     X
23		BG   scroll MSB     X
24		BG   LSB RAM offset     40h * 40h  (0-0fff)
25		BG   MSB RAM offset
30		FG   scroll LSB   < Y >
31		FG   scroll MSB   < Y >
32		FG   scroll LSB     X
33		FG   scroll MSB     X
34		FG   LSB RAM offset     40h * 40h  (0-0fff)
35		FG   MSB RAM offset
40		spare scroll LSB  < Y >  (Not used)
41		spare scroll MSB  < Y >  (Not used)
5a-5c	Control registers
		bits 7-4 always 0
		bits 3-1 select the control signal to drive.
		bit   0  is the value passed to the control signal.
5a		data
		00-01	INT line to TMS320C10 DSP (Active low trigger)
		0c-0d	lockout for coin A input (Active low lockout)
		0e-0f	lockout for coin B input (Active low lockout)
5c		data
		00-01	???
		02-03	???
		04-05	Active low INTerrupt to Z80(0) for screen refresh
		06-07	Flip Screen (Active high flips)
		08-09	Background RAM display bank switch
		0a-0b	Foreground ROM display bank switch (not used here)
		0c-0d	??? (what the hell does this do ?)
60		LSB data to char display layer
61		MSB data to char display layer
62		LSB data to BG   display layer
63		MSB data to BG   display layer
64		LSB data to FG   display layer
65		MSB data to FG   display layer
70		ROM bank selector for Z80(0) address 8000-ffff
		data
		00  switch ROM from 8000-ffff out, and put sprite/palette/sound RAM back.
		02  switch lower half of B25-18.ROM  ROM to 8000-ffff
		03  switch upper half of B25-18.ROM  ROM to 8000-ffff
		04  switch lower half of B25-19.ROM  ROM to 8000-ffff
		05  switch upper half of B25-19.ROM  ROM to 8000-ffff
		07  switch               B25-30.ROM  ROM to 8000-ffff



Z80:(1)  Sound CPU
0000-7fff Main ROM
8000-807f RAM ???
c000-cfff Sound RAM , $C000-C7FF shared with $C000-C7FF in Z80(0) ram



TMS320C10 DSP: Harvard type architecture. RAM and ROM on seperate data buses.
0000-05ff ROM 16-bit opcodes (word access only). Moved to $8000-8bff for
				 MAME compatibility. View this ROM in the debugger at $8000h
0000-0090 Internal RAM (words).

in:
01		data read from addressed Z80:(0) address space (Main RAM/Sprite RAM)

out:
00		address of Z80:(0) to read/write to
01		data to write to addressed Z80:(0) address space (Main RAM/Sprite RAM)
03		bit 15 goes to BIO line of TMS320C10. BIO is a polled input line.

-


[Dec/06/1999]

Wardna no Mori (Wardner JPN Ver.)
(c)1987 Toaplan
TP-009

b25-05.bin      16384 bytes  be36a53e
b25-06.bin      16384 bytes  3bfeb6ae
b25-07.bin      16384 bytes  50e329e0
b25-17.bin      32768 bytes  4164dca9
b25-20.bin      32768 bytes  1113ad38



[01/07/2000]

        PYROS   CHIP PLACEMENT

USES TWO Z80 CPU'S W/YM3812 SOUND

CHIP #  POSITION  TYPE
----------------------
08       F12      27256
09       F14       "
10       F15       "
11       F16       "
12       F18       "
13       F19       "
14       F21       "
15       F23       "
16       K4        "
29       6M        "
30       10M       "
33       7F        "
34       9F        "
35       11F       "
18       7M       27512
19       8M        "
01       D15       "
02       D16       "
03       D17       "
04       D19       "


ROMs 33, 34 and 35 have been cut to 16KB files (second halves are empty).


-



