Zilog Z80 Intruction set definition (undocumented features are included)
------------------------------------------------------------------------

abbreviation definition used in the different columns of the instruction set table:

prefixes:
i		DD or FD prefix, it changes the role of H, L or HL (HL -> IX/IY; H -> XH/YH; L-> XL/YL)
CB		prefix for bit/rotate instructions
ED		prefix for special instructions
d		a signed byte displacement constant (comes before (!) the opcode at DD+CB or FD+CB prefix)

bits in the opcodes:
x		do not care bit in the opcode
rrr/ppp		register operand (value 110 [memory pointer] is excluded)
iii/jjj		register operand used with DD/FD prefix (value 110 [memory pointer] is excluded)
rr/pp		register pair operand
ii/jj/kk	register pair operand with DD/FD prefix
cc/ccc		condition
bbb		bit number
aaa		restart address of RST instruction

parameters:
n		single byte constant
n n		two byte constant (LSB first, MSB next)
d		a signed byte displacement constant used with IX/IY registers
e		a signed byte constant at relative jumps

operands in the instruction followed by the mnemonik
r		register operand determined by the rrr bits of the opcode
p		register operand determined by the ppp bits of the opcode
i		register operand determiner by DD/FD prefix and the iii bits of the opcode
j		register operand determiner by DD/FD prefix and the iii bits of the opcode
ii		register pair operand determined by DD/FD prefix and the ii bits of the opcode
jj		register pair operand determined by DD/FD prefix (IX or IY instead of HL)
kk		register pair operand determined by DD/FD prefix and the kk bits of the opcode
pp		register pair operand determined by the pp bits of the opcode
rr		register pair operand determined by the rr bits of the opcode
n		single byte constant
nn		two byte constant
d		a signed byte displacement constant used with IX/IY registers
e		a signed byte constant at relative jumps
b		bit number determined by the bbb bits of the opcode
c		condition determined by the cc or ccc bits of the opcode
add		restart address of RST instruction determined by the aaa bits of the opcode

bits of the flag register (SZ5H3PNC):
.		unaffected flag bit, instruction does not change the flag bit
0		instruction clears the flag bit
1		instruction sets the flag bit
S		sign flag bit is affected, highest bit of the result; 0=positive, 1=negative
Z		zero flag bit is affected; 0=nonzero result, 1=result is zero
5		undocumented flag bit is copied from bit 5 of the 8 bit result
H		half carry flag bit is set; high, if there is carry or borrow between result bits 3 and 4
3		undocumented flag bit is copied from bit 3 of the 8 bit result
P		Parity/Overflow flag bit is affected according to parity of the result; 0:odd, 1:even
V		Parity/Overflow flag bit is affected according to overflow to the sign bit
N		Add/Substract flag bit is affected; 0=add/increment 1=substract/decrement
C		Carry/Borrow flag bit is affected; high in carry/borrow situation
?		the flag bit is affected in special way, in some cases notes column specifies it

Decode tables for the different objects:

===========================================================
3bits	rrr	ppp	iii	jjj	ccc	aaa	bbb
-----------------------------------------------------------
000	B	B	B	B	NZ	00h	  0
001	C	C	C	C	Z	08h	  1
010	D	D	D	D	NC	10h	  2
011	E	E	E	E	C	18h	  3
100	H	H	XH/YH	XH/YH	PO	20h	  4
101	L	L	XL/YL	XL/YL	PE	28h	  5
110	-	-	-	-	P	30h	  6
111	A	A	A	A	M	38h	  7
===========================================================

==========================================
2bits	rr	pp	ii	kk	cc
------------------------------------------
00	BC	BC	BC	BC	NZ
01	DE	DE	DE	DE	Z
10	HL	HL	IX/IY	IX/IY	NC
11	SP	AF	SP	AF	C
==========================================
Instruction set table:

========================================================================================================================
Prefix OpCode	Params	SZ5H3PNC	Cycle	Instruction		Notes
========================================================================================================================
. .. . 00000000 . .	........	 4	NOP
. .. . 01110110 . .	........	 4	HALT
. .. . 11110011 . .	........	 4	DI
. .. . 11111011 . .	........	 4	EI
. .. . 00111111 . .	..5H3.0C	 4	CCF			flag 5 and 3 are set based on (A or F); flag H <- not C			
. .. . 00110111 . .	..503.01	 4	SCF			flag 5 and 3 are set based on the result of (A or F)
. .. . 00100111 . .	SZ5H3P.C	 4	DAA
. .. . 00101111 . .	..513.1.	 4	CPL

. .. . 01rrrppp . .	........	 4	LD  r,p
. .. . 01110rrr . .	........	 7	LD  (HL),r
. .. . 01rrr110 . .	........	 7	LD  r,(HL)
i .. . 01iiijjj . .	........	 8	LD  i,j
i .. . 01110rrr d .	........	19	LD  (jj+d),r
i .. . 01rrr110 d .	........	19	LD  r,(jj+d)
. .. . 00rrr110 n .	........	 7	LD  r,n
i .. . 00iii110 n .	........	11	LD  i,n
. .. . 00110110 n .	........	10	LD  (HL),n
i .. . 00110110 d n	........	19	LD  (jj+d),n

. .. . 00001010 . .	........	 7	LD  A,(BC)
. .. . 00011010 . .	........	 7	LD  A,(DE)
. .. . 00000010 . .	........	 7	LD  (BC),A
. .. . 00010010 . .	........	 7	LD  (DE),A
. .. . 00111010 n n	........	13	LD  A,(nn)
. .. . 00110010 n n	........	13	LD  (nn),A

. .. . 00rr0001 n n	........	10	LD  rr,nn
i .. . 00ii0001 n n	........	14	LD  ii,nn
. .. . 00101010 n n	........	16	LD  HL,(nn)
i .. . 00101010 n n	........	20	LD  jj,(nn)
. .. . 00100010 n n	........	16	LD  (nn),HL
i .. . 00100010 n n	........	20	LD  (nn),jj
. .. . 11111001 . .	........	 6	LD  SP,HL
i .. . 11111001 . .	........	10	LD  SP,jj

. .. . 11101011 . .	........	 4	EX  DE,HL		DD/FD prefix is not changing HL to IX/IY
. .. . 00001000 . .	????????	 4	EX  AF,AF'
. .. . 11011001 . .	........	 4	EXX
. .. . 11100011 . .	........	19	EX  (SP),HL
i .. . 11100011 . .	........	23	EX  (SP),jj

. .. . 11pp0101 . .	........	11	PUSH pp
i .. . 11kk0101 . .	........	15	PUSH kk
. .. . 11pp0001 . .	........	10	POP  pp			if pp=AF, flags are changed
i .. . 11kk0001 . .	........	14	POP  kk			if kk=AF, flags are changed

. .. . 10000rrr . .	SZ5H3V0C	 4	ADD A,r
. .. . 10001rrr . .	SZ5H3V0C	 4	ADC A,r
. .. . 10010rrr . .	SZ5H3V1C	 4	SUB r
. .. . 10011rrr . .	SZ5H3V1C	 4	SBC r
. .. . 10100rrr . .	SZ513P00	 4	AND r
. .. . 10101rrr . .	SZ503P00	 4	XOR r
. .. . 10110rrr . .	SZ503P00	 4	OR  r
. .. . 10111rrr . .	SZ5H3V1C	 4	CP  r			flag 5 an 3 are set based on 'r'

. .. . 10000110 . .	SZ5H3V0C	 7	ADD A,(HL)
. .. . 10001110 . .	SZ5H3V0C	 7	ADC A,(HL)
. .. . 10010110 . .	SZ5H3V1C	 7	SUB (HL)
. .. . 10011110 . .	SZ5H3V1C	 7	SBC (HL)
. .. . 10100110 . .	SZ513P00	 7	AND (HL)
. .. . 10101110 . .	SZ503P00	 7	XOR (HL)
. .. . 10110110 . .	SZ503P00	 7	OR  (HL)
. .. . 10111110 . .	SZ5H3V1C	 7	CP  (HL)		flag 5 an 3 are set based on (HL)

i .. . 10000iii . .	SZ5H3V0C	 8	ADD A,i
i .. . 10001iii . .	SZ5H3V0C	 8	ADC A,i
i .. . 10010iii . .	SZ5H3V1C	 8	SUB i
i .. . 10011iii . .	SZ5H3V1C	 8	SBC i
i .. . 10100iii . .	SZ513P00	 8	AND i
i .. . 10101iii . .	SZ503P00	 8	XOR i
i .. . 10110iii . .	SZ503P00	 8	OR  i
i .. . 10111iii . .	SZ5H3V1C	 8	CP  i			flag 5 an 3 are set based on 'i'
                            
i .. . 10000110 d .	SZ5H3V0C	19	ADD A,(jj+d)
i .. . 10001110 d .	SZ5H3V0C	19	ADC A,(jj+d)
i .. . 10010110 d .	SZ5H3V1C	19	SUB (jj+d)
i .. . 10011110 d .	SZ5H3V1C	19	SBC (jj+d)
i .. . 10100110 d .	SZ513P00	19	AND (jj+d)
i .. . 10101110 d .	SZ503P00	19	XOR (jj+d)
i .. . 10110110 d .	SZ503P00	19	OR  (jj+d)
i .. . 10111110 d .	SZ5H3V1C	19	CP  (jj+d)		flag 5 an 3 are set based on (jj+d)

. .. . 11000110 n .	SZ5H3V0C	 7	ADD A,n
. .. . 11001110 n .	SZ5H3V0C	 7	ADC A,n
. .. . 11010110 n .	SZ5H3V1C	 7	SUB n
. .. . 11011110 n .	SZ5H3V1C	 7	SBC n
. .. . 11100110 n .	SZ513P00	 7	AND n
. .. . 11101110 n .	SZ503P00	 7	XOR n
. .. . 11110110 n .	SZ503P00	 7	OR  n
. .. . 11111110 n .	SZ5H3V1C	 7	CP  n			flag 5 an 3 are set based on 'n'

. .. . 00rrr100 . .	SZ5H3V0.	 4	INC r
. .. . 00rrr101 . .	SZ5H3V1.	 4	DEC r
i .. . 00iii100 . .	SZ5H3V0.	 8	INC i
i .. . 00iii101 . .	SZ5H3V1.	 8	DEC i
. .. . 00110100 . .	SZ5H3V0.	11	INC (HL)
. .. . 00110101 . .	SZ5H3V1.	11	DEC (HL)
i .. . 00110100 d .	SZ5H3V0.	26	INC (jj+d)
i .. . 00110101 d .	SZ5H3V1.	26	DEC (jj+d)

. .. . 00rr1001 . .	..5H3.0C	11	ADD HL,rr		flags H, 5 and 3 are set based on the high byte of result
i .. . 00ii1001 . .	..5H3.0C	15	ADD jj,ii		flags H, 5 and 3 are set based on the high byte of result

. .. . 00rr0011 . .	........	 6	INC rr
. .. . 00rr1011 . .	........	 6	DEC rr
i .. . 00ii0011 . .	........	10	INC ii
i .. . 00ii1011 . .	........	10	DEC ii

. .. . 00000111 . .     ..503.0C	 4	RLCA
. .. . 00010111 . .     ..503.0C	 4	RLA
. .. . 00001111 . .     ..503.0C	 4	RRCA
. .. . 00011111 . .     ..503.0C	 4	RRA

. .. . 11000011 n n	........	10	JP nn
. .. . 11ccc010 n n	........	10	JP c,nn
. .. . 00011000 e	........	12	JR e
. .. . 001cc000 e	........	 7/12	JR c,e
. .. . 11101001 . .	........	 4	JP (HL)
i .. . 11101001 . .	........	 8	JP (ii)
. .. . 00010000 e .	........	10/13	DJNZ e
. .. . 11001101 n n	........	17	CALL nn
. .. . 11ccc100 n n	........	10/17	CALL c,nn
. .. . 11001001 . .	........	10	RET
. .. . 11ccc000 . .	........	 5/17	RET c
. .. . 11aaa111 . .	........	17	RST add

. .. . 11011011 n .	........	11	IN A,(n)
. .. . 11010011 n .	........	11	OUT (n),A
------------------------------------------------------------------------------------------------------------------------
. ED . 01rr1011 n n	........	20	LD  rr,(nn)
. ED . 01rr0011 n n	........	20	LD  (nn),rr
. ED . 01010111 . .	SZ503?0.	 9	LD  A,I			flag P <- IIF2
. ED . 01011111 . .	SZ503?0.	 9	LD  A,R			flag P <- IIF2
. ED . 01000111 . .	........	 9	LD  I,A
. ED . 01001111 . .	........	 9	LD  R,A

. ED . 01xxx100 . .	SZ5H3V1C	 8	NEG			(documented: x=0)
. ED . 01x0x110 . .	........	 8	IM 0			(documented: x=0)
. ED . 01x10110 . .	........	 8	IM 1			(documented: x=0)
. ED . 01x11110 . .	........	 8	IM 2			(documented: x=0)
. ED . 01xx0101 . .	........	14	RETN			(documented: x=0)
. ED . 01001101 . .	........	14	RETI
. ED . 01011101 . .	........	14	RETN			(undocumented)
. ED . 011x1101 . .	........	14	RETN			(undocumented)

. ED . 01rr1010 . .	SZ5H3V0C	15	ADC HL,rr		flags H, 5 and 3 are set based on the high byte of result
. ED . 01rr0010 . .	SZ5H3V1C	15	SBC HL,rr		flags H, 5 and 3 are set based on the high byte of result
. ED . 01101111 . .	SZ503P0.	18	RLD
. ED . 01100111 . .	SZ503P0.	18	RRD

. ED . 01rrr000 . .	SZ503P0.	12	IN  r,(C)
. ED . 01110000 . .	SZ503P0.	12	IN  F,(C)
. ED . 01rrr001 . .	........	12	OUT (C),r
. ED . 01110001 . .	........	12	OUT (C),0

. ED . 10100000 . .	..?0?P..	16	LDI			Flag P=0 if BC=0
. ED . 10110000 . .	..?0?0..	16/21	LDIR
. ED . 10101000 . .	..?0?P..	16	LDD			Flag P=0 if BC=0
. ED . 10111000 . .	..?0?0..	16/21	LDDR
. ED . 10100001 . .	?Z?0?P1.	16	CPI			Flag P=0 if BC=0
. ED . 10110001 . .	?Z?0?P1.	16/21	CPIR			Flag P=0 if BC=0
. ED . 10101001 . .	?Z?0?P1.	16	CPD			Flag P=0 if BC=0
. ED . 10111001 . .	?Z?0?P1.	16/21	CPDR			Flag P=0 if BC=0
. ED . 10100010 . .	SZ5?3???	16	INI			Flags S, Z, 3 and 5 are set according to B
. ED . 10110010 . .	010?0???	16/21	INIR
. ED . 10101010 . .	SZ5?3???	16	IND			Flags S, Z, 3 and 5 are set according to B
. ED . 10111010 . .	010?0???	16/21	INDR
. ED . 10101011 . .	SZ5?3???	16	OUTD			Flags S, Z, 3 and 5 are set according to B
. ED . 10111011 . .	010?0???	16/21	OTDR
. ED . 10100011 . .	SZ5?3???	16	OUTI			Flags S, Z, 3 and 5 are set according to B
. ED . 10110011 . .	010?0???	16/21	OTIR
------------------------------------------------------------------------------------------------------------------------
. CB . 00000rrr . .     SZ503P0C	 8	RLC r
. CB . 00001rrr . .     SZ503P0C	 8	RRC r
. CB . 00010rrr . .     SZ503P0C	 8	RL  r
. CB . 00011rrr . .     SZ503P0C	 8	RR  r
. CB . 00100rrr . .     SZ503P0C	 8	SLA r
. CB . 00101rrr . .     SZ503P0C	 8	SRA r
. CB . 00110rrr . .     SZ503P0C	 8	SLL r			set bit 0 to 1
. CB . 00111rrr . .     SZ503P0C	 8	SRL r

. CB . 00000110 . .     SZ503P0C	15	RLC (HL)
. CB . 00001110 . .     SZ503P0C	15	RRC (HL)
. CB . 00010110 . .     SZ503P0C	15	RL  (HL)
. CB . 00011110 . .     SZ503P0C	15	RR  (HL)
. CB . 00100110 . .     SZ503P0C	15	SLA (HL)
. CB . 00101110 . .     SZ503P0C	15	SRA (HL)
. CB . 00110110 . .     SZ503P0C	15	SLL (HL)		set bit 0 to 1
. CB . 00111110 . .     SZ503P0C	15	SRL (HL)

i CB d 00000rrr . .     SZ503P0C	23	RLC (jj+d),r		the result of RLC (jj+d) is also loaded into 'r'
i CB d 00001rrr . .     SZ503P0C	23	RRC (jj+d),r		the result of RLC (jj+d) is also loaded into 'r'
i CB d 00010rrr . .     SZ503P0C	23	RL  (jj+d),r		the result of RL  (jj+d) is also loaded into 'r'
i CB d 00011rrr . .     SZ503P0C	23	RR  (jj+d),r		the result of RR  (jj+d) is also loaded into 'r'
i CB d 00100rrr . .     SZ503P0C	23	SLA (jj+d),r		the result of SLA (jj+d) is also loaded into 'r'
i CB d 00101rrr . .     SZ503P0C	23	SRA (jj+d),r		the result of SRA (jj+d) is also loaded into 'r'
i CB d 00110rrr . .     SZ503P0C	23	SLL (jj+d),r		the result of SLL (jj+d) is also loaded into 'r'
									bit 0 is set to 1
i CB d 00111rrr . .     SZ503P0C	23	SRL (jj+d),r		the result of SRL (jj+d) is also loaded into 'r'

i CB d 00000110 . .     SZ503P0C	23	RLC (jj+d)
i CB d 00001110 . .     SZ503P0C	23	RRC (jj+d)
i CB d 00010110 . .     SZ503P0C	23	RL  (jj+d)
i CB d 00011110 . .     SZ503P0C	23	RR  (jj+d)
i CB d 00100110 . .     SZ503P0C	23	SLA (jj+d)
i CB d 00101110 . .     SZ503P0C	23	SRA (jj+d)
i CB d 00110110 . .     SZ503P0C	23	SLL (jj+d)		set bit 0 to 1
i CB d 00111110 . .     SZ503P0C	23	SRL (jj+d)

. CB . 01bbbrrr . .	SZ513Z0.	 8	BIT b,r			flag S is set, if bit 7 is set and b=7
. CB . 10bbbrrr . .	........	 8	RES b,r
. CB . 11bbbrrr . .	........	 8	SET b,r

. CB . 01bbb110 . .	SZ?1?Z0. (*)	12	BIT b,(HL)		flag S is set, if bit 7 is set and b=7
									flag 5 & 3 are set an undocumented temporary register
. CB . 10bbb110 . .	........	15	RES b,(HL)
. CB . 11bbb110 . .	........	15	SET b,(HL)

i CB d 01bbbxxx . .	SZ513Z0.	20	BIT b,(jj+d)		flag S is set, if bit 7 is set and b=7
i CB d 10bbbrrr . .	........	23	RES b,(jj+d),r		the result of SET b,(jj+d) is also loaded into 'r'
i CB d 11bbbrrr . .	........	23	SET b,(jj+d),r		the result of RES b,(jj+d) is also loaded into 'r'

i CB d 01bbb110 . .	SZ513Z0.	20	BIT b,(jj+d)		flag S is set, if bit 7 is set and b=7
i CB d 10bbb110 . .	........	23	RES b,(jj+d)
i CB d 11bbb110 . .	........	23	SET b,(jj+d)
========================================================================================================================

(*) after flag bits:	flag 3 & 5 is not implemented in the emulator