# LIB: pm_init

Initialize Pokemon-Mini and provide common declarations

pm_init.s

Type: Header File

Dependency: None

Including Rules: Must be on top of the main file

ROM/RAM Usage: None

## Initialization

When the extra flag IRQF_NOSTARTUP isn't expecified in PM_HEADER, the following will be executed:

1. Interrupts are disabled
2. Upper addresses (Indexes) are cleared
3. Register N and stack are initialized
4. Upper address of map and sprite bases are set to 0
5. Seed of rand is set to 1
6. Interrupts enable are all cleared
7. Interrupts priorities set: PRC=1, Timers=2, Tmr256=1, Cartridge=3, Keypad=1, IR/Shock=2
8. Jump to main

Otherwise only step 8 is executed.

## Macros

Note: Macros names are case insensitive

Macro | Description
--- | ---
PM_HEADER game_title, irq_flags, ex_flags | Declare pokémon-mini header, ROM start game_title = Maximum of 12 Characters irq_flags = or IRQ_* flags ex_flags = or IRQF_* flags
PM_ROMINFO | Optional, report ROM and RAM size, must be included on the bottom of the main file.
CPU_CLEAR | Clear BCD and NIBBLE modes
COLORPM_INIT | Initialize Color PM Interface
RIRQ rirq_flag | Return from IRQ, single IRQ_* only
PRIORITY_IRQS priority, irqs_select | Setup IRQ priorities, multiple IRQ_* allowed priority = 0 - IRQs Disabled priority = 1 - Low Priority priority = 2 - Medium Priority priority = 3 - High Priority
ENABLE_IRQS irqs_select | Enable IRQ(s), multiple IRQ_* allowed
DISABLE_IRQS irqs_select | Disable IRQ(s), multiple IRQ_* allowed
ENABLE_MIRQ | Enable Master Interrupt, same as "and f, ~FLAG_ID"
DISABLE_MIRQ | Disable Master Interrupt, same as "or f, FLAG_ID"
PM_ALIGN_MAP PM_ALIGN_TILES | Align data for PRC map tiles, equivalent to ".align 8" but doesn't override assembler's aligment
PM_ALIGN_SPR PM_ALIGN_OAM | Align data for PRC sprites tiles, equivalent to ".align 64" but doesn't override assembler's aligment

Peudo-instructions, automatically manage banks before jumping:

Macro | Description
--- | ---
fjmp label | Far version of JMP
fjc label | Far version of JC
fjnc label | Far version of JNC
fjz label | Far version of JZ
fjnz label | Far version of JNZ
fjdbnz label | Far version of JBDNZ
fjl label | Far version of JL
fjle label | Far version of JLE
fjg label | Far version of JG
fjge label | Far version of JGE
fjo label | Far version of JO
fjno label | Far version of JNO
fjns label | Far version of JNS
fjs label | Far version of JS
fcall label | Far version of CALL
fcallc label | Far version of CALLC
fcallnc label | Far version of CALLNC
fcallz label | Far version of CALLZ
fcallnz label | Far version of CALLNZ
fcalll label | Far version of CALLL
fcallle label | Far version of CALLLE
fcallg label | Far version of CALLG
fcallge label | Far version of CALLGE
fcallo label | Far version of CALLO
fcallno label | Far version of CALLNO
fcallns label | Far version of CALLNS
fcalls label | Far version of CALLS

Peudo-instructions, automatically update upper address:

Macro | Description
--- | ---
add24x number | Add/Sub XI:X by number
add24y number | Add/Sub YI:Y by number
add24hl number | Add/Sub I:HL by number
add24x_a number | Add/Sub XI:X by number, trash A on page cross
add24y_a number | Add/Sub YI:Y by number, trash A on page cross
add24hl_a number | Add/Sub I:HL by number, trash A on page cross

number value must be between -65535 and 65535
"INC" instruction will be used if number is 1
No code will be generated if number is 0

## Defines

Definitions in bold have multiple definitions with the same value, hover the mouse over to see the list

### RAM variables

Definition | Init | Description
--- | --- | ---
PMINIT_RAND | 0x0001 | 16-Bits Random Generator Seed
PMINIT_KEYPAD | 0x?? | Keypad status at start of ROM
PMINIT_FRAMECNT | 0x00 | Frame counter, used in CLib PRC wait routines

### Memory bases

Definition | Value | Description
--- | --- | ---
Registers bases |  |
SSTACK_BASE | $1FFC | Safe stack base (for RAM vector)
STACK_BASE | $2000 | Stack base
REG_BASE | $2000 | Registers base
N_BASE | $20 | N register base
Memory bases |  |
VRAM_BASE | $1000 | Videobuffer RAM base
SPR_BASE | $1300 | Sprites base
MAP_BASE | $1360 | MAP base
RAM_BASE | $1500 | RAM base
PRC_MAP_BASE | $2082 | PRC Map base
PRC_SPR_BASE | $2085 | PRC Sprite base
Version |  |
PMINIT_VER | 5 | pminit library revision number

### Registers

For more information about registers, check here

Definition | Value | Description
--- | --- | ---
BIOS |  |
SYS_CTRL1 | $00 | System Control 1
SYS_CTRL2 | $01 | System Control 2
SYS_CTRL3 | $02 | System Control 3
Seconds Timer |  |
SEC_CTRL | $08 | Second Counter Control
SEC_CNT_LO | $09 | Second Counter Low
SEC_CNT_MID | $0A | Second Counter Middle
SEC_CNT_HI | $0B | Second Counter High
Battery status |  |
SYS_BATT | $10 | Battery Sensor
Timers control |  |
TMR1_SCALE | $18 | Timer 1 Prescalar
TMR1_ENA_OSC | $19 | Timers Osc. Enable Timer 1 Osc. Select
TMR2_SCALE | $1A | Timer 2 Prescalar
TMR2_OSC | $1B | Timer 2 Osc. Select
TMR3_SCALE | $1C | Timer 3 Prescalar
TMR3_OSC | $1D | Timer 3 Osc. Select
Interrupts |  |
IRQ_PRI1 | $20 | IRQ Priority 1
IRQ_PRI2 | $21 | IRQ Priority 2
IRQ_PRI3 | $22 | IRQ Priority 3
IRQ_ENA1 | $23 | IRQ Enable 1
IRQ_ENA2 | $24 | IRQ Enable 2
IRQ_ENA3 | $25 | IRQ Enable 3
IRQ_ENA4 | $26 | IRQ Enable 4
IRQ_ACT1 | $27 | IRQ Active 1
IRQ_ACT2 | $28 | IRQ Active 2
IRQ_ACT3 | $29 | IRQ Active 3
IRQ_ACT4 | $2A | IRQ Active 4
Timer 1 |  |
TMR1_CTRL_L | $30 | Timer 1 Control (Lo)
TMR1_CTRL_H | $31 | Timer 1 Control (Hi)
TMR1_PRE_L | $32 | Timer 1 Preset (Lo)
TMR1_PRE_H | $33 | Timer 1 Preset (Hi)
TMR1_PVT_L | $34 | Timer 1 Pivot (Lo)
TMR1_PVT_H | $35 | Timer 1 Pivot (Hi)
TMR1_CNT_L | $36 | Timer 1 Count (Lo)
TMR1_CNT_H | $37 | Timer 1 Count (Hi)
Timer 2 |  |
TMR2_CTRL_L | $38 | Timer 2 Control (Lo)
TMR2_CTRL_H | $39 | Timer 2 Control (Hi)
TMR2_PRE_L | $3A | Timer 2 Preset (Lo)
TMR2_PRE_H | $3B | Timer 2 Preset (Hi)
TMR2_PVT_L | $3C | Timer 2 Pivot (Lo)
TMR2_PVT_H | $3D | Timer 2 Pivot (Hi)
TMR2_CNT_L | $3E | Timer 2 Count (Lo)
TMR2_CNT_H | $3F | Timer 2 Count (Hi)
256 Hz Timer |  |
TMR256_CTRL | $40 | 256Hz Timer Control
TMR256_CNT | $41 | 256Hz Timer Counter
Timer 3 |  |
TMR3_CTRL_L | $48 | Timer 3 Control (Lo)
TMR3_CTRL_H | $49 | Timer 3 Control (Hi)
TMR3_PRE_L | $4A | Timer 3 Preset (Lo)
TMR3_PRE_H | $4B | Timer 3 Preset (Hi)
TMR3_PVT_L | $4C | Timer 3 Pivot (Lo)
TMR3_PVT_H | $4D | Timer 3 Pivot (Hi)
TMR3_CNT_L | $4E | Timer 3 Count (Lo)
TMR3_CNT_H | $4F | Timer 3 Count (Hi)
Inputs |  |
KEY_PAD | $52 | Key-Pad Status (Active 0)
CART_BUS | $53 | Cart Bus
IO |  |
IO_DIR | $60 | I/O Direction Select
IO_DATA | $61 | I/O Data Register
Audio |  |
AUD_CTRL | $70 | Audio Control
AUD_VOL | $71 | Audio Volume
PRC |  |
PRC_MODE | $80 | PRC Stage Control
PRC_RATE | $81 | PRC Rate Control
PRC_MAP_LO | $82 | PRC Map Tile Base Low
PRC_MAP_MID | $83 | PRC Map Tile Base Middle
PRC_MAP_HI | $84 | PRC Map Tile Base High
PRC_SCROLL_Y | $85 | PRC Map Vertical Scroll
PRC_SCROLL_X | $86 | PRC Map Horizontal Scroll
PRC_SPR_LO | $87 | PRC Sprite Tile Base Low
PRC_SPR_MID | $88 | PRC Sprite Tile Base Middle
PRC_SPR_HI | $89 | PRC Sprite Tile Base High
PRC_CNT | $8A | PRC Counter
PokeMini |  |
POKEMINI_CHR | $D0 | Debug output a character
POKEMINI_HEX | $D1 | Debug output a 8-bits hexadecimal
POKEMINI_UINTB | $D2 | Debug output a unsigned 8-bits number
POKEMINI_SINTB | $D3 | Debug output a signed 8-bits number
POKEMINI_UINTWL | $D4 | Debug output a unsigned 16-bits number (Low Byte)
POKEMINI_UINTWH | $D5 | Debug output a unsigned 16-bits number (High Byte)
POKEMINI_SINTWL | $D6 | Debug output a signed 16-bits number (Low Byte)
POKEMINI_SINTWH | $D7 | Debug output a signed 16-bits number (High Byte)
POKEMINI_FX8_8 | $DE | Debug output a fixed point 8.8 number (Low Byte)
POKEMINI_FX8_8H | $DF | Debug output a fixed point 8.8 number (High Byte)
Color PM Interface |  |
COLORPM_CMD | $F0 | Color PM Command, writing send a command. Reading will check unlock status: $00 (Locked), $CE (Unlocked)
COLORPM_ADDR | $F1 | CVRAM Address (Low Byte)
COLORPM_ADDRH | $F2 | CVRAM Address (High Byte)
COLORPM_DATA | $F3 | CVRAM Data
COLORPM_LP0 | $F4 | Low Nibble Pixel 0 Color
COLORPM_HP0 | $F5 | High Nibble Pixel 0 Color
COLORPM_LP1 | $F6 | Low Nibble Pixel 1 Color
COLORPM_HP1 | $F7 | Hig Nibble Pixel 1 Color
LCD Raw |  |
LCD_CTRL | $FE | LCD Raw Control Byte
LCD_DATA | $FF | LCD Raw Data Byte

### Misc. defines

Definitions to be used to comunicate with the hardware
For more information about registers, check here

Definition | Value | Usage | Description
--- | --- | --- | ---
Master Interrupt |  |  |
DISABLE_IRQ | $C0 | mov f, DISABLE_IRQ | Disable Master Interrupt
ENABLE_IRQ | $80 | mov f, ENABLE_IRQ | Enable Master Interrupt
Timers Enable |  |  |
TMRS_ENABLE | $30 | or [n+TMR1_ENA_OSC], TMRS_ENABLE | Timers Enable
|  | and [n+TMR1_ENA_OSC], ~TMRS_ENABLE | Timers Disable
TMRS_OSC1 | $20 | or [n+TMR1_ENA_OSC], TMRS_OSC1 | Timers 2Mhz Oscillator On
|  | and [n+TMR1_ENA_OSC], ~TMRS_OSC1 | Timers 2Mhz Oscillator Off
TMRS_OSC2 | $10 | or [n+TMR1_ENA_OSC], TMRS_OSC2 | Timers 32Khz Oscillator On
|  | and [n+TMR1_ENA_OSC], ~TMRS_OSC2 | Timers 32Khz Oscillator Off
Seconds Timer |  |  |
SEC_ENABLE | $01 | or [n+SEC_CTRL], SEC_ENABLE | Second Counter Enable
|  | and [n+SEC_CTRL], ~SEC_ENABLE | Second Counter Disable
SEC_RESET | $02 | or [n+SEC_CTRL], SEC_RESET | Second Counter Reset
Battery status |  |  |
LOW_BATTERY | $20 | tst [n+SYS_BATT], LOW_BATTERY | Low battery indicator
256Hz Timer |  |  |
TMR256_ENABLE | $01 | or [n+TMR256_CTRL], TMR256_ENABLE | 256Hz Timer Enable
|  | and [n+TMR256_CTRL], ~TMR256_ENABLE | 256Hz Timer Disable
TMR256_RESET | $02 | or [n+TMR256_CTRL], TMR256_RESET | 256Hz Timer Reset
Timer 1-3 Control |  |  |
TMR_8BITS | $00 | mov [n+TMR1_CTRL_L], TMR8_BITS | .. mov [n+TMR2_CTRL_L], TMR8_BITS | .. mov [n+TMR3_CTRL_L], TMR8_BITS | .. | 8-Bits Timer 1-3
TMR_16BITS | $80 | mov [n+TMR1_CTRL_L], TMR16_BITS | .. mov [n+TMR2_CTRL_L], TMR16_BITS | .. mov [n+TMR3_CTRL_L], TMR16_BITS | .. | 16-Bits Timer 1-3
TMR_PRESET | $02 | or [n+TMR1_CTRL_L], TMR_PRESET or [n+TMR1_CTRL_H],TMR_PRESET or [n+TMR2_CTRL_L],TMR_PRESET or [n+TMR2_CTRL_H],TMR_PRESET or [n+TMR3_CTRL_L],TMR_PRESET or [n+TMR3_CTRL_H],TMR_PRESET | Timer 1-3 Preset
TMR_ENABLE | $04 | mov [n+TMR1_CTRL_L], TMR_ENABLE | .. mov [n+TMR1_CTRL_H], TMR_ENABLE | .. mov [n+TMR2_CTRL_L], TMR_ENABLE | .. mov [n+TMR2_CTRL_H], TMR_ENABLE | .. mov [n+TMR3_CTRL_L], TMR_ENABLE | .. mov [n+TMR3_CTRL_H], TMR_ENABLE | .. | Timer 1-3 Enable
Timer 1-3 Scale |  |  |
TMR_DIV_OFF | $00 | mov [n+TMR1_SCALE], TMR_DIV_OFF mov [n+TMR2_SCALE], TMR_DIV_OFF mov [n+TMR3_SCALE], TMR_DIV_OFF | Prescalar Off
TMR_DIV_2 | $08 | mov [n+TMR1_SCALE], TMR_DIV_2 mov [n+TMR2_SCALE], TMR_DIV_2 mov [n+TMR3_SCALE], TMR_DIV_2 | Prescalar /2 (Osc. 1)
TMR_DIV_8 | $09 | mov [n+TMR1_SCALE], TMR_DIV_8 mov [n+TMR2_SCALE], TMR_DIV_8 mov [n+TMR3_SCALE], TMR_DIV_8 | Prescalar /8 (Osc. 1)
TMR_DIV_32 | $0A | mov [n+TMR1_SCALE], TMR_DIV_32 mov [n+TMR2_SCALE], TMR_DIV_32 mov [n+TMR3_SCALE], TMR_DIV_32 | Prescalar /32 (Osc. 1)
TMR_DIV_64 | $0B | mov [n+TMR1_SCALE], TMR_DIV_64 mov [n+TMR2_SCALE], TMR_DIV_64 mov [n+TMR3_SCALE], TMR_DIV_64 | Prescalar /64 (Osc. 1)
TMR_DIV_128 | $0C | mov [n+TMR1_SCALE], TMR_DIV_128 mov [n+TMR2_SCALE], TMR_DIV_128 mov [n+TMR3_SCALE], TMR_DIV_128 | Prescalar /128 (Osc. 1)
TMR_DIV_256 | $0D | mov [n+TMR1_SCALE], TMR_DIV_256 mov [n+TMR2_SCALE], TMR_DIV_256 mov [n+TMR3_SCALE], TMR_DIV_256 | Prescalar /256 (Osc. 1)
TMR_DIV_1024 | $0E | mov [n+TMR1_SCALE], TMR_DIV_1024 mov [n+TMR2_SCALE], TMR_DIV_1024 mov [n+TMR3_SCALE], TMR_DIV_1024 | Prescalar /1024 (Osc. 1)
TMR_DIV_4096 | $0F | mov [n+TMR1_SCALE], TMR_DIV_4096 mov [n+TMR2_SCALE], TMR_DIV_4096 mov [n+TMR3_SCALE], TMR_DIV_4096 | Prescalar /4096 (Osc. 1)
TMR_DIV2_OFF | $00 | mov [n+TMR1_SCALE], TMR_DIV2_OFF mov [n+TMR2_SCALE], TMR_DIV2_OFF mov [n+TMR3_SCALE], TMR_DIV2_OFF | Prescalar Off
TMR_DIV2_1 | $08 | mov [n+TMR1_SCALE], TMR_DIV2_1 mov [n+TMR2_SCALE], TMR_DIV2_1 mov [n+TMR3_SCALE], TMR_DIV2_1 | Prescalar /1 (Osc. 2)
TMR_DIV2_2 | $09 | mov [n+TMR1_SCALE], TMR_DIV2_2 mov [n+TMR2_SCALE], TMR_DIV2_2 mov [n+TMR3_SCALE], TMR_DIV2_2 | Prescalar /2 (Osc. 2)
TMR_DIV2_4 | $0A | mov [n+TMR1_SCALE], TMR_DIV2_4 mov [n+TMR2_SCALE], TMR_DIV2_4 mov [n+TMR3_SCALE], TMR_DIV2_4 | Prescalar /4 (Osc. 2)
TMR_DIV2_8 | $0B | mov [n+TMR1_SCALE], TMR_DIV2_8 mov [n+TMR2_SCALE], TMR_DIV2_8 mov [n+TMR3_SCALE], TMR_DIV2_8 | Prescalar /8 (Osc. 2)
TMR_DIV2_16 | $0C | mov [n+TMR1_SCALE], TMR_DIV2_16 mov [n+TMR2_SCALE], TMR_DIV2_16 mov [n+TMR3_SCALE], TMR_DIV2_16 | Prescalar /16 (Osc. 2)
TMR_DIV2_32 | $0D | mov [n+TMR1_SCALE], TMR_DIV2_32 mov [n+TMR2_SCALE], TMR_DIV2_32 mov [n+TMR3_SCALE], TMR_DIV2_32 | Prescalar /32 (Osc. 2)
TMR_DIV2_64 | $0E | mov [n+TMR1_SCALE], TMR_DIV2_64 mov [n+TMR2_SCALE], TMR_DIV2_64 mov [n+TMR3_SCALE], TMR_DIV2_64 | Prescalar /64 (Osc. 2)
TMR_DIV2_128 | $0F | mov [n+TMR1_SCALE], TMR_DIV2_128 mov [n+TMR2_SCALE], TMR_DIV2_128 mov [n+TMR3_SCALE], TMR_DIV2_128 | Prescalar /128 (Osc. 2)
TMR_HI_DIV_OFF | $00 | mov [n+TMR1_SCALE], TMR_HI_DIV_OFF | .. mov [n+TMR2_SCALE], TMR_HI_DIV_OFF | .. mov [n+TMR3_SCALE], TMR_HI_DIV_OFF | .. | Prescalar Off
TMR_HI_DIV_2 | $80 | mov [n+TMR1_SCALE], TMR_HI_DIV_2 | .. mov [n+TMR2_SCALE], TMR_HI_DIV_2 | .. mov [n+TMR3_SCALE], TMR_HI_DIV_2 | .. | Prescalar /2 (Osc. 1)
TMR_HI_DIV_8 | $90 | mov [n+TMR1_SCALE], TMR_HI_DIV_8 | .. mov [n+TMR2_SCALE], TMR_HI_DIV_8 | .. mov [n+TMR3_SCALE], TMR_HI_DIV_8 | .. | Prescalar /8 (Osc. 1)
TMR_HI_DIV_32 | $A0 | mov [n+TMR1_SCALE], TMR_HI_DIV_32 | .. mov [n+TMR2_SCALE], TMR_HI_DIV_32 | .. mov [n+TMR3_SCALE], TMR_HI_DIV_32 | .. | Prescalar /32 (Osc. 1)
TMR_HI_DIV_64 | $B0 | mov [n+TMR1_SCALE], TMR_HI_DIV_64 | .. mov [n+TMR2_SCALE], TMR_HI_DIV_64 | .. mov [n+TMR3_SCALE], TMR_HI_DIV_64 | .. | Prescalar /64 (Osc. 1)
TMR_HI_DIV_128 | $C0 | mov [n+TMR1_SCALE], TMR_HI_DIV_128 | .. mov [n+TMR2_SCALE], TMR_HI_DIV_128 | .. mov [n+TMR3_SCALE], TMR_HI_DIV_128 | .. | Prescalar /128 (Osc. 1)
TMR_HI_DIV_256 | $D0 | mov [n+TMR1_SCALE], TMR_HI_DIV_256 | .. mov [n+TMR2_SCALE], TMR_HI_DIV_256 | .. mov [n+TMR3_SCALE], TMR_HI_DIV_256 | .. | Prescalar /256 (Osc. 1)
TMR_HI_DIV_1024 | $E0 | mov [n+TMR1_SCALE], TMR_HI_DIV_1024 | .. mov [n+TMR2_SCALE], TMR_HI_DIV_1024 | .. mov [n+TMR3_SCALE], TMR_HI_DIV_1024 | .. | Prescalar /1024 (Osc. 1)
TMR_HI_DIV_4096 | $F0 | mov [n+TMR1_SCALE], TMR_HI_DIV_4096 | .. mov [n+TMR2_SCALE], TMR_HI_DIV_4096 | .. mov [n+TMR3_SCALE], TMR_HI_DIV_4096 | .. | Prescalar /4096 (Osc. 1)
TMR_HI_DIV2_OFF | $00 | mov [n+TMR1_SCALE], TMR_HI_DIV2_OFF | .. mov [n+TMR2_SCALE], TMR_HI_DIV2_OFF | .. mov [n+TMR3_SCALE], TMR_HI_DIV2_OFF | .. | Prescalar Off
TMR_HI_DIV2_1 | $80 | mov [n+TMR1_SCALE], TMR_HI_DIV2_1 | .. mov [n+TMR2_SCALE], TMR_HI_DIV2_1 | .. mov [n+TMR3_SCALE], TMR_HI_DIV2_1 | .. | Prescalar /1 (Osc. 2)
TMR_HI_DIV2_2 | $90 | mov [n+TMR1_SCALE], TMR_HI_DIV2_2 | .. mov [n+TMR2_SCALE], TMR_HI_DIV2_2 | .. mov [n+TMR3_SCALE], TMR_HI_DIV2_2 | .. | Prescalar /2 (Osc. 2)
TMR_HI_DIV2_4 | $A0 | mov [n+TMR1_SCALE], TMR_HI_DIV2_4 | .. mov [n+TMR2_SCALE], TMR_HI_DIV2_4 | .. mov [n+TMR3_SCALE], TMR_HI_DIV2_4 | .. | Prescalar /4 (Osc. 2)
TMR_HI_DIV2_8 | $B0 | mov [n+TMR1_SCALE], TMR_HI_DIV2_8 | .. mov [n+TMR2_SCALE], TMR_HI_DIV2_8 | .. mov [n+TMR3_SCALE], TMR_HI_DIV2_8 | .. | Prescalar /8 (Osc. 2)
TMR_HI_DIV2_16 | $C0 | mov [n+TMR1_SCALE], TMR_HI_DIV2_16 | .. mov [n+TMR2_SCALE], TMR_HI_DIV2_16 | .. mov [n+TMR3_SCALE], TMR_HI_DIV2_16 | .. | Prescalar /16 (Osc. 2)
TMR_HI_DIV2_32 | $D0 | mov [n+TMR1_SCALE], TMR_HI_DIV2_32 | .. mov [n+TMR2_SCALE], TMR_HI_DIV2_32 | .. mov [n+TMR3_SCALE], TMR_HI_DIV2_32 | .. | Prescalar /32 (Osc. 2)
TMR_HI_DIV2_64 | $E0 | mov [n+TMR1_SCALE], TMR_HI_DIV2_64 | .. mov [n+TMR2_SCALE], TMR_HI_DIV2_64 | .. mov [n+TMR3_SCALE], TMR_HI_DIV2_64 | .. | Prescalar /64 (Osc. 2)
TMR_HI_DIV2_128 | $F0 | mov [n+TMR1_SCALE], TMR_HI_DIV2_128 | .. mov [n+TMR2_SCALE], TMR_HI_DIV2_128 | .. mov [n+TMR3_SCALE], TMR_HI_DIV2_128 | .. | Prescalar /128 (Osc. 2)
Timer 1-3 Osc. Select |  |  |
TMR_OSC1_LO | $00 | mov [n+TMR1_OSC], TMR_OSC1_LO | .. mov [n+TMR2_OSC], TMR_OSC1_LO | .. mov [n+TMR3_OSC], TMR_OSC1_LO | .. | Timer 1-3 Osc. 1 for Lo / 16Bits
TMR_OSC1_HI | $00 | mov [n+TMR1_OSC], TMR_OSC1_HI | .. mov [n+TMR2_OSC], TMR_OSC1_HI | .. mov [n+TMR3_OSC], TMR_OSC1_HI | .. | Timer 1-3 Osc. 1 for Hi
TMR_OSC2_LO | $01 | mov [n+TMR1_OSC], TMR_OSC2_LO | .. mov [n+TMR2_OSC], TMR_OSC2_LO | .. mov [n+TMR3_OSC], TMR_OSC2_LO | .. | Timer 1-3 Osc. 2 for Lo / 16Bits
TMR_OSC2_HI | $02 | mov [n+TMR1_OSC], TMR_OSC2_HI | .. mov [n+TMR2_OSC], TMR_OSC2_HI | .. mov [n+TMR3_OSC], TMR_OSC2_HI | .. | Timer 1-3 Osc. 2 for Hi
Interrupts Priority |  |  |
IRQ_PRI1_TMR3 | $03 | mov [n+IRQ_PRI1],IRQ_PRI1_TMR3| .. | IRQ Priority - Timer 3
IRQ_PRI1_TMR1 | $0C | mov [n+IRQ_PRI1],IRQ_PRI1_TMR1| .. | IRQ Priority - Timer 1
IRQ_PRI1_TMR2 | $30 | mov [n+IRQ_PRI1] ,IRQ_PRI1_TMR2| .. | IRQ Priority - Timer 2
IRQ_PRI1_PRC | $C0 | mov [n+IRQ_PRI1], IRQ_PRI1_PRC| .. | IRQ Priority - PRC
IRQ_PRI2_UNKNOWN | $03 | mov [n+IRQ_PRI2], IRQ_PRI2_UNKNOWN| .. | IRQ Priority - Unknown
IRQ_PRI2_KEY_PAD | $0C | mov [n+IRQ_PRI2], IRQ_PRI2_KEY_PAD| .. | IRQ Priority - Keypad
IRQ_PRI2_CARTRIDGE | $30 | mov [n+IRQ_PRI2], IRQ_PRI2_CARTRIDGE| .. | IRQ Priority - Cartridge
IRQ_PRI2_TMR256 | $C0 | mov [n+IRQ_PRI2], IRQ_PRI2_TMR256| .. | IRQ Priority - 256 Hz Timer
IRQ_PRI3_IO | $03 | mov [n+IRQ_PRI3], IRQ_PRI3_IO| .. | IRQ Priority - I/O
Interrupts Enable |  |  |
IRQ_ENA1_TMR3_PVT | $01 | mov [n+IRQ_ENA1], IRQ_ENA1_TMR3_PVT| .. | IRQ Enable - Timer 3 Pivot
IRQ_ENA1_TMR3_HI | $02 | mov [n+IRQ_ENA1], IRQ_ENA1_TMR3_HI| .. | IRQ Enable - Timer 3 Upper-8
IRQ_ENA1_TMR1_LO | $04 | mov [n+IRQ_ENA1], IRQ_ENA1_TMR1_LO| .. | IRQ Enable - Timer 1 Lower-8
IRQ_ENA1_TMR1_HI | $08 | mov [n+IRQ_ENA1], IRQ_ENA1_TMR1_HI| .. | IRQ Enable - Timer 1 Upper-8
IRQ_ENA1_TMR2_LO | $10 | mov [n+IRQ_ENA1], IRQ_ENA1_TMR2_LO| .. | IRQ Enable - Timer 2 Lower-8
IRQ_ENA1_TMR2_HI | $20 | mov [n+IRQ_ENA1], IRQ_ENA1_TMR2_HI| .. | IRQ Enable - Timer 2 Upper-8
IRQ_ENA1_PRC_DIV | $40 | mov [n+IRQ_ENA1], IRQ_ENA1_PRC_DIV| .. | IRQ Enable - PRC Frame Divider
IRQ_ENA1_PRC_COPY | $80 | mov [n+IRQ_ENA1], IRQ_ENA1_PRC_COPY| .. | IRQ Enable - PRC Frame Copy
IRQ_ENA2_CARTRIDGE | $01 | mov [n+IRQ_ENA2], IRQ_ENA2_CARTRIDGE| .. | IRQ Enable - Cartridge IRQ
IRQ_ENA2_CART_EJECT | $02 | mov [n+IRQ_ENA2], IRQ_ENA2_CARTRIDGE| .. | IRQ Enable - Cartridge Eject
IRQ_ENA2_1HZ | $04 | mov [n+IRQ_ENA2], IRQ_ENA2_1HZ| .. | IRQ Enable - 1Hz (From 256 Hz Timer)
IRQ_ENA2_2HZ | $08 | mov [n+IRQ_ENA2], IRQ_ENA2_2HZ| .. | IRQ Enable - 2 Hz (From 256 Hz Timer)
IRQ_ENA2_8HZ | $10 | mov [n+IRQ_ENA2], IRQ_ENA2_8HZ| .. | IRQ Enable - 8 Hz (From 256 Hz Timer)
IRQ_ENA2_32HZ | $20 | mov [n+IRQ_ENA2], IRQ_ENA2_32HZ| .. | IRQ Enable - 32 Hz (From 256 Hz Timer)
IRQ_ENA3_KEY_A | $01 | mov [n+IRQ_ENA3], IRQ_ENA3_KEY_A| .. | IRQ Enable - A Key
IRQ_ENA3_KEY_B | $02 | mov [n+IRQ_ENA3], IRQ_ENA3_KEY_B| .. | IRQ Enable - B Key
IRQ_ENA3_KEY_C | $04 | mov [n+IRQ_ENA3], IRQ_ENA3_KEY_C| .. | IRQ Enable - C Key
IRQ_ENA3_KEY_UP | $08 | mov [n+IRQ_ENA3], IRQ_ENA3_KEY_UP| .. | IRQ Enable - Up Key
IRQ_ENA3_KEY_DOWN | $10 | mov [n+IRQ_ENA3], IRQ_ENA3_KEY_DOWN| .. | IRQ Enable - Down Key
IRQ_ENA3_KEY_LEFT | $20 | mov [n+IRQ_ENA3], IRQ_ENA3_KEY_LEFT| .. | IRQ Enable - Left Key
IRQ_ENA3_KEY_RIGHT | $40 | mov [n+IRQ_ENA3], IRQ_ENA3_KEY_RIGHT| .. | IRQ Enable - Right Key
IRQ_ENA3_KEY_POWER | $80 | mov [n+IRQ_ENA3], IRQ_ENA3_KEY_POWER| .. | IRQ Enable - Power Key
IRQ_ENA3_KEYS | $FF | mov [n+IRQ_ENA3], IRQ_ENA3_KEYS | IRQ Enable - All Keys
IRQ_ENA4_UNKNOWN1 | $01 | mov [n+IRQ_ENA4], IRQ_ENA4_UNKNOWN1 | IRQ Enable - Unknown 1
IRQ_ENA4_UNKNOWN2 | $02 | mov [n+IRQ_ENA4], IRQ_ENA4_UNKNOWN2 | IRQ Enable - Unknown 2
IRQ_ENA4_UNKNOWN3 | $04 | mov [n+IRQ_ENA4], IRQ_ENA4_UNKNOWN3 | IRQ Enable - Unknown 3
IRQ_ENA4_UNMAPPED1 | $10 | mov [n+IRQ_ENA4], IRQ_ENA4_UNMAPPED1 | IRQ Enable - Unmapped 1
IRQ_ENA4_UNMAPPED2 | $20 | mov [n+IRQ_ENA4], IRQ_ENA4_UNMAPPED2 | IRQ Enable - Unmapped 2
IRQ_ENA4_SHOCK | $40 | mov [n+IRQ_ENA4], IRQ_ENA4_SHOCK | IRQ Enable - Shock Detector
IRQ_ENA4_IR_RX | $80 | mov [n+IRQ_ENA4], IRQ_ENA4_IR_RX | IRQ Enable - IR Receiver
Interrupts Active |  |  |
IRQ_ACT1_TMR3_PVT | $01 | mov [n+IRQ_ACT1], IRQ_ACT1_TMR3_PVT| .. | IRQ Active - Timer 3 Pivot
IRQ_ACT1_TMR3_HI | $02 | mov [n+IRQ_ACT1], IRQ_ACT1_TMR3_HI| .. | IRQ Active - Timer 3 Upper-8
IRQ_ACT1_TMR1_LO | $04 | mov [n+IRQ_ACT1], IRQ_ACT1_TMR1_LO| .. | IRQ Active - Timer 1 Lower-8
IRQ_ACT1_TMR1_HI | $08 | mov [n+IRQ_ACT1], IRQ_ACT1_TMR1_HI| .. | IRQ Active - Timer 1 Upper-8
IRQ_ACT1_TMR2_LO | $10 | mov [n+IRQ_ACT1], IRQ_ACT1_TMR2_LO| .. | IRQ Active - Timer 2 Lower-8
IRQ_ACT1_TMR2_HI | $20 | mov [n+IRQ_ACT1], IRQ_ACT1_TMR2_HI| .. | IRQ Active - Timer 2 Upper-8
IRQ_ACT1_PRC_DIV | $40 | mov [n+IRQ_ACT1], IRQ_ACT1_PRC_DIV| .. | IRQ Active - PRC Frame Divider
IRQ_ACT1_PRC_COPY | $80 | mov [n+IRQ_ACT1], IRQ_ACT1_PRC_COPY| .. | IRQ Active - PRC Frame Copy
IRQ_ACT2_CARTRIDGE | $01 | mov [n+IRQ_ACT2], IRQ_ACT2_CARTRIDGE| .. | IRQ Active - Cartridge IRQ
IRQ_ACT2_CART_EJECT | $02 | mov [n+IRQ_ACT2], IRQ_ACT2_CARTRIDGE| .. | IRQ Active - Cartridge Eject
IRQ_ACT2_1HZ | $04 | mov [n+IRQ_ACT2], IRQ_ACT2_1HZ| .. | IRQ Active - 1Hz (From 256 Hz Timer)
IRQ_ACT2_2HZ | $08 | mov [n+IRQ_ACT2], IRQ_ACT2_2HZ| .. | IRQ Active - 2 Hz (From 256 Hz Timer)
IRQ_ACT2_8HZ | $10 | mov [n+IRQ_ACT2], IRQ_ACT2_8HZ| .. | IRQ Active - 8 Hz (From 256 Hz Timer)
IRQ_ACT2_32HZ | $20 | mov [n+IRQ_ACT2], IRQ_ACT2_32HZ| .. | IRQ Active - 32 Hz (From 256 Hz Timer)
IRQ_ACT3_KEY_A | $01 | mov [n+IRQ_ACT3], IRQ_ACT3_KEY_A| .. | IRQ Active - A Key
IRQ_ACT3_KEY_B | $02 | mov [n+IRQ_ACT3], IRQ_ACT3_KEY_B| .. | IRQ Active - B Key
IRQ_ACT3_KEY_C | $04 | mov [n+IRQ_ACT3], IRQ_ACT3_KEY_C| .. | IRQ Active - C Key
IRQ_ACT3_KEY_UP | $08 | mov [n+IRQ_ACT3], IRQ_ACT3_KEY_UP| .. | IRQ Active - Up Key
IRQ_ACT3_KEY_DOWN | $10 | mov [n+IRQ_ACT3], IRQ_ACT3_KEY_DOWN| .. | IRQ Active - Down Key
IRQ_ACT3_KEY_LEFT | $20 | mov [n+IRQ_ACT3], IRQ_ACT3_KEY_LEFT| .. | IRQ Active - Left Key
IRQ_ACT3_KEY_RIGHT | $40 | mov [n+IRQ_ACT3], IRQ_ACT3_KEY_RIGHT| .. | IRQ Active - Right Key
IRQ_ACT3_KEY_POWER | $80 | mov [n+IRQ_ACT3], IRQ_ACT3_KEY_POWER| .. | IRQ Active - Power Key
IRQ_ACT3_KEYS | $FF | mov [n+IRQ_ACT3], IRQ_ACT3_KEYS | IRQ Active - All Keys
IRQ_ACT4_UNKNOWN1 | $01 | mov [n+IRQ_ACT4], IRQ_ACT4_UNKNOWN1 | IRQ Active - Unknown 1
IRQ_ACT4_UNKNOWN2 | $02 | mov [n+IRQ_ACT4], IRQ_ACT4_UNKNOWN2 | IRQ Active - Unknown 2
IRQ_ACT4_UNKNOWN3 | $04 | mov [n+IRQ_ACT4], IRQ_ACT4_UNKNOWN3 | IRQ Active - Unknown 3
IRQ_ACT4_UNMAPPED1 | $10 | mov [n+IRQ_ACT4], IRQ_ACT4_UNMAPPED1 | IRQ Active - Unmapped 1
IRQ_ACT4_UNMAPPED2 | $20 | mov [n+IRQ_ACT4], IRQ_ACT4_UNMAPPED2 | IRQ Active - Unmapped 2
IRQ_ACT4_SHOCK | $40 | mov [n+IRQ_ACT4], IRQ_ACT4_SHOCK | IRQ Active - Shock Detector
IRQ_ACT4_IR_RX | $80 | mov [n+IRQ_ACT4], IRQ_ACT4_IR_RX | IRQ Active - IR Receiver
Keypad Input |  |  |
KEY_A | $01 | tst [n+KEY_PAD], KEY_A | A Key (Active Low)
KEY_B | $02 | tst [n+KEY_PAD], KEY_B | B Key (Active Low)
KEY_C | $04 | tst [n+KEY_PAD], KEY_C | C Key (Active Low)
KEY_UP | $08 | tst [n+KEY_PAD], KEY_UP | Up Key (Active Low)
KEY_DOWN | $10 | tst [n+KEY_PAD], KEY_DOWN | Down Key (Active Low)
KEY_LEFT | $20 | tst [n+KEY_PAD], KEY_LEFT | Left Key (Active Low)
KEY_RIGHT | $40 | tst [n+KEY_PAD], KEY_RIGHT | Right Key (Active Low)
KEY_POWER | $80 | tst [n+KEY_PAD], KEY_POWER | Power Key (Active Low)
Parallel I/O |  | IO_DIR: 0 = Output / 1 = Input |
IO_IR_TX | $01 | mov [n+IO_DIR], IO_IR_TX| .. mov [n+IO_DATA], IO_IR_TX| .. | IR Transmitter
IO_IR_RX | $02 | mov [n+IO_DIR], IO_IR_RX| .. mov [n+IO_DATA], IO_IR_RX| .. | IR Receiver
IO_EEPROM_DAT | $04 | mov [n+IO_DIR], IO_EEPROM_DAT| .. mov [n+IO_DATA], IO_EEPROM_DAT| .. | EEPROM Data
IO_EEPROM_CLK | $08 | mov [n+IO_DIR], IO_EEPROM_CLK| .. mov [n+IO_DATA], IO_EEPROM_CLK| .. | EEPROM Clock
IO_RUMBLE | $10 | mov [n+IO_DIR], IO_RUMBLE| .. mov [n+IO_DATA], IO_RUMBLE| .. | Rumble
IO_IR_DISABLE | $20 | mov [n+IO_DIR], IO_IR_DISABLE| .. mov [n+IO_DATA], IO_IR_DISABLE| .. | IR Disable
PRC Mode |  |  |
PRC_INVERTMAP | $01 | mov [n+PRC_MODE], PRC_INVERTMAP| .. | PRC Mode - Invert Map
PRC_ENABLEMAP | $02 | mov [n+PRC_MODE], PRC_ENABLEMAP| .. | PRC Mode - Enable Map
PRC_ENABLESPR | $04 | mov [n+PRC_MODE], PRC_ENABLESPR| .. | PRC Mode - Enable Sprite
PRC_ENABLE | $08 | mov [n+PRC_MODE], PRC_ENABLE| .. | PRC Mode - Enable
PRC_MAP12X16 | $00 | mov [n+PRC_MODE], PRC_MAP12X16| .. | PRC Mode - 12 x 16 Map
PRC_MAP16X12 | $10 | mov [n+PRC_MODE], PRC_MAP16X12| .. | PRC Mode - 16 x 12 Map
PRC_MAP24X8 | $20 | mov [n+PRC_MODE], PRC_MAP24X8| .. | PRC Mode - 24 x 8 Map
PRC_MAP24X16 | $30 | mov [n+PRC_MODE], PRC_MAP24X16| .. | PRC Mode - 24 x 16 Map
PRC_MAPMASK | $30 | mov [n+PRC_MODE], ~PRC_MAPMASK or [n+PRC_MODE], PRC_MAPnXn... | PRC Mode - Map Mask
PRC Rate |  |  |
PRC_RATE_3 | $00 | mov [n+PRC_RATE], PRC_RATE_3| .. | PRC Rate - /3, 24 fps
PRC_RATE_6 | $02 | mov [n+PRC_RATE], PRC_RATE_6| .. | PRC Rate - /6, 12 fps
PRC_RATE_9 | $04 | mov [n+PRC_RATE], PRC_RATE_9| .. | PRC Rate - /9, 8 fps
PRC_RATE_12 | $06 | mov [n+PRC_RATE], PRC_RATE_12| .. | PRC Rate - /12, 6 fps
PRC_RATE_2 | $08 | mov [n+PRC_RATE], PRC_RATE_2| .. | PRC Rate - /2, 36 fps
PRC_RATE_4 | $0A | mov [n+PRC_RATE], PRC_RATE_4| .. | PRC Rate - /4, 18 fps
PRC_RATE_6ALT | $0C | mov [n+PRC_RATE], PRC_RATE_6ALT| .. | PRC Rate - /6, 12 fps
PRC_RATE_8 | $0E | mov [n+PRC_RATE], PRC_RATE_8| .. | PRC Rate - /8, 9 fps
PRC_RATEMASK | $0E | and [n+PRC_RATE], ~PRC_RATEMASK or [n+PRC_RATE], PRC_RATE_n | PRC Rate - Mask
LCD Data |  |  |
LCD_COLUMN_LO | $00 | mov [n+LCD_CTRL], LCD_COLUMN_LO + #n | LCD - Set Column Low
LCD_COLUMN_HI | $10 | mov [n+LCD_CTRL], LCD_COLUMN_HI + #n | LCD - Set Column High
LCD_STARTLINE | $40 | mov [n+LCD_CTRL], LCD_STARTLINE + #n | LCD - Set Start line
LCD_PAGE | $B0 | mov [n+LCD_CTRL], LCD_PAGE + #n | LCD - Set Page
LCD_CONTRAST | $81 | mov [n+LCD_CTRL], LCD_CONTRAST mov [n+LCD_DATA], #n | LCD - Set Contrast
LCD_SEGDIR | $A0 | mov [n+LCD_CTRL], LCD_SEGDIR | LCD - Segment Direction (Normal)
LCD_INVSEGDIR | $A1 | mov [n+LCD_CTRL], LCD_INVSEGDIR | LCD - Segment Direction (Inverted)
LCD_DISPSEL_ON | $A4 | mov [n+LCD_CTRL], LCD_DISPSEL_ON | LCD - Display Selection On
LCD_DISPSEL_OFF | $A5 | mov [n+LCD_CTRL], LCD_DISPSEL_OFF | LCD - Display Selection Off
LCD_DISPINV_ON | $A6 | mov [n+LCD_CTRL], LCD_DISPINV_ON | LCD - Display Invert On
LCD_DISPINV_OFF | $A7 | mov [n+LCD_CTRL], LCD_DISPINV_OFF | LCD - Display Invert Off
LCD_DISPENABLE | $AE | mov [n+LCD_CTRL], LCD_DISPENABLE | LCD - Display Enable
LCD_DISPDISABLE | $AF | mov [n+LCD_CTRL], LCD_DISPDISABLE | LCD - Display Disable
LCD_ROWNORMAL | $C0 | mov [n+LCD_CTRL], LCD_ROWNORMAL | LCD - Row Normal
LCD_ROWINVERT | $C4 | mov [n+LCD_CTRL], LCD_ROWINVERT | LCD - Row Inverted
LCD_START_RMW | $E0 | mov [n+LCD_CTRL], LCD_START_RMW | LCD - Start Read-Modify-Write
LCD_END_RMW | $EE | mov [n+LCD_CTRL], LCD_END_RMW | LCD - End Read-Modify-Write
LCD_RESET | $E2 | mov [n+LCD_CTRL], LCD_RESET | LCD - Reset
LCD_NOP | $E3 | mov [n+LCD_CTRL], LCD_NOP | LCD - No Operation
Color PM Interface |  |  |
COLORPM_UNLOCK1 | $5A | mov [n+COLORPM_CMD], COLORPM_UNLOCK1 | 1st Unlock Code
COLORPM_UNLOCK2 | $CE | mov [n+COLORPM_CMD], COLORPM_UNLOCK2 | 2nd Unlock Code
COLORPM_UNLOCKED | $CE | mov a, COLORPM_UNLOCKED cmp a, [n+COLORPM_CMD] ; Zero if Color PM Interface is unlocked | Check if Color PM interface is unlocked
COLORPM_LOCK | $CF | mov [n+COLORPM_CMD], COLORPM_LOCK | Lock Color PM interface
COLORPM_FIXED | $A0 | mov [n+COLORPM_CMD], COLORPM_FIXED | Set CVRAM Access fixed Address won't change when data R/W
COLORPM_POSTINC | $A1 | mov [n+COLORPM_CMD], COLORPM_POSTINC | Set CVRAM Access post-increment Address add 1 after data R/W
COLORPM_POSTDEC | $A2 | mov [n+COLORPM_CMD], COLORPM_POSTINC | Set CVRAM Access post-decrement Address subtract 1 after data R/W
COLORPM_PREINC | $A3 | mov [n+COLORPM_CMD], COLORPM_POSTINC | Set CVRAM Access pre-increment Address add 1 before data R/W
COLORPM_VRAM_ON | $D0 | mov [n+COLORPM_CMD], COLORPM_VRAM_ON | Enable VRAM updates Any access to VRAM will update CVRAM
COLORPM_LCD_ON | $D1 | mov [n+COLORPM_CMD], COLORPM_LCD_ON | Enable LCD updates Any access to LCD will update CVRAM
COLORPM_PRC_ON | $D2 | mov [n+COLORPM_CMD], COLORPM_PRC_ON | Enable PRC updates Any PRC rendering will update CVRAM
COLORPM_VRAM_OFF | $D8 | mov [n+COLORPM_CMD], COLORPM_VRAM_OFF | Disable VRAM updates Any access to VRAM will be ignored
COLORPM_LCD_OFF | $D9 | mov [n+COLORPM_CMD], COLORPM_LCD_OFF | Disable LCD updates Any access to LCD will be ignred
COLORPM_PRC_OFF | $DA | mov [n+COLORPM_CMD], COLORPM_PRC_OFF | Disable PRC updates Any PRC rendering will be ignored
COLORPM_FLIP | $F0 | mov [n+COLORPM_CMD], COLORPM_FLIP | Flip CVRAM page

### Sprites

Sprites should be updated after IRQ_PRC_COPY.

Definition | Value | Usage | Description
--- | --- | --- | ---
Sprite Content |  |  |
SPR_X | $00 | mov x, #sprite_id << 2 mov [x+SPR_X], a | Sprite X Position Starting from -16
SPR_Y | $01 | mov x, #sprite_id << 2 mov [x+SPR_Y], a | Sprite Y Position Starting from -16
SPR_TILE | $02 | mov x, #sprite_id << 2 mov [x+SPR_TILE], a | Sprite Tile Number 0 to 255
SPR_CTRL | $03 | mov x, #sprite_id << 2 mov [x+SPR_CTRL], a | Sprite Control
Sprite Control |  |  |
SPR_HFLIP | $01 | mov a, SPR_HFLIP|.. mov [x+SPR_CTRL], a | Sprite Horizontal Flip
SPR_VFLIP | $02 | mov a, SPR_VFLIP|.. mov [x+SPR_CTRL], a | Sprite Vertical Flip
SPR_INVERT | $04 | mov a, SPR_INVERT|.. mov [x+SPR_CTRL], a | Sprite Invert Pixels
SPR_ENABLE | $08 | mov a, SPR_ENABLE|.. mov [x+SPR_CTRL], a | Sprite Enabled (Visible)

### Call BIOS IRQs

This defines are used on CINT instruction

Definition | Value | Description
--- | --- | ---
CINT_HARDRESET | $00 | Hard Reset
CINT_SOFTRESET | $01 | Soft Reset
CINT_SOFTRESET2 | $02 | Soft Reset
CINT_PRC_COPY | $03 | IRQ PRC Copy Complete
CINT_PRC_DIV | $04 | IRQ PRC Frame Divider Overflow
CINT_TMR2_HI | $05 | Timer 2 Upper-8 Overflow
CINT_TMR2_LO | $06 | Timer 2 Lower-8 Overflow (8b only)
CINT_TMR1_HI | $07 | Timer 1 Upper-8 Overflow
CINT_TMR1_LO | $08 | Timer 1 Lower-8 Overflow (8b only)
CINT_TMR3_HI | $09 | Timer 3 Upper-8 Overflow
CINT_TMR3_PVT | $0A | Timer 3 Pivot
CINT_32HZ | $0B | 32Hz (From 256 Hz Timer)
CINT_8HZ | $0C | 8Hz (From 256 Hz Timer)
CINT_2HZ | $0D | 2Hz (From 256 Hz Timer)
CINT_1HZ | $0E | 1Hz (From 256 Hz Timer)
CINT_IR_RX | $0F | IR Receiver
CINT_SHOCK | $10 | Shock Sensor
CINT_CART_EJECT | $13 | Cartridge Eject
CINT_CARTRIDGE | $14 | Cartridge IRQ
CINT_KEY_POWER | $15 | Power Key
CINT_KEY_RIGHT | $16 | Right Key
CINT_KEY_LEFT | $17 | Left Key
CINT_KEY_DOWN | $18 | Down Key
CINT_KEY_UP | $19 | Up Key
CINT_KEY_C | $1A | C Key
CINT_KEY_B | $1B | B Key
CINT_KEY_A | $1C | A Key
CINT_UNKNOWN1D | $1D | Unknown $1D
CINT_UNKNOWN1E | $1E | Unknown $1E
CINT_UNKNOWN1F | $1F | Unknown $1F
CINT_IRQ_FFF1 | $20 | User IRQ Routine at PC 0xFFF1
CINT_SUSPEND | $21 | Suspend System
CINT_SLEEP_LCDOFF | $22 | Sleep ??
CINT_SLEEP_LCDON | $23 | Sleep with display on ??
CINT_SHUTDOWN | $24 | Shutdown System (Use this to exit your game!)
CINT_UNKNOWN25 | $25 | ?? (Involves Cartridge Eject)
CINT_SET_CONTRAST | $26 | Set default LCD Constrast A = Contrast level 0x00 to 0x3F
CINT_ADD_CONTRAST | $27 | Increase or decrease Contrast based of Zero flag 0 = Increase, 1 = Decrease Return A = 0x00 if succeed, 0xFF if not.
CINT_APPLY_CONTRAST | $28 | Apply default LCD Constrast
CINT_GET_CONTRAST | $29 | Get default LCD Contrast return A
CINT_TMP_CONTRAST | $2A | Set temporary LCD Constrast A = Contrast level 0x00 to 0x3F
CINT_LCD_ON | $2B | Turn LCD On
CINT_LCD_INIT | $2C | Initialize LCD
CINT_LCD_OFF | $2D | Turn LCD Off
CINT_ENABLE_RAMVECTOR | $2E | Enable RAM vector. (Check if Register 0x01 Bit 7 is set, if not, it set bit 6 and 7)
CINT_DISABLE_RAMVECTOR | $2F | Disable RAM vector
CINT_ENABLE_CART_EJECT | $30 | Disable Cart Eject IRQ 13 (with abort)
CINT_DISABLE_CART_EJECT | $31 | Enable Cart Eject IRQ 13 (with abort)
CINT_UNKNOWN32 | $32 | ?? (Involves Cartridge Eject)
CINT_UNKNOWN33 | $33 | ?? (Involves Cartridge Eject)
CINT_UNKNOWN34 | $34 | Nintendo Dev Card (??)
CINT_UNKNOWN35 | $35 | Nintendo Dev Card (??)
CINT_UNKNOWN36 | $36 | ?? (Involves Cartridge Eject)
CINT_UNKNOWN37 | $37 | Disable Cartridge Eject IRQ (Reg 0x24, Bit 1 = 0)
CINT_UNKNOWN38 | $38 | ?? (Involves Cartridge Eject)
CINT_UNKNOWN39 | $39 | ?? (Involves Cartridge Eject)
CINT_UNKNOWN3A | $3A | Rumored to speed up CPU?
CINT_CART_DISABLE | $3B | Recover from IRQ $39?
CINT_CART_ENABLE | $3C | Cart power on and update state
CINT_CART_DETECT | $3D | Cart detect. Z: No cart, NZ: Cart inserted (Test Register 0x53 Bit 1 and invert Zero flag)
CINT_ROUTINE | $3E | Read structure, write 0xFF, compare values and optionally jump to subroutine
    X point to a structure in memory:
    structure {
      byte   type            ; 0x01 = Call subroutine
                             ; 0x00 = Don't call subroutine
      triple write_0xFF_addr ; Address that 0xFF will be written
      triple compare_addr    ; Address to read for compare
      byte   compare_value   ; Value that must match the compare
      triple subroutine      ; Use byte POP to receive flag of the compare
    }
    if type is 0x00, register A return 0x01 if compare is equal
CINT_SET_PRC_RATE | $3F | Set PRC Rate A = 0 to 7
CINT_GET_PRC_RATE | $40 | Get PRC Rate Return A
CINT_MULTICART | $41 | Test cart type. Returns Z: non multi cart, NZ: multi cart (Register 0x01 Bit 3)
CINT_DEVCART_READID | $42 | Nintendo Dev Card (Read IDs)
CINT_DEVCART_RESET | $43 | Nintendo Dev Card (Reset)
CINT_DEVCART_PROGRAM | $44 | Nintendo Dev Card (Program Byte)
CINT_DEVCART_ERASE | $45 | Nintendo Dev Card (Erase Sector)
CINT_DEVCART_UNLOCK | $46 | Nintendo Dev Card (Unlock flash page register. Command 0xD0)
CINT_DEVCART_BANK | $47 | Nintendo Dev Card (Select flash bank. A=bank Nr, X last address of flash page)
CINT_DEVCART_CMD_C9 | $48 | Nintendo Dev Card (Command 0xC9)
CINT_DEVCART_PREPID | $49 | Nintendo Dev Card (Prepare Manufacturer and device ID readout. Command 0xC0)
CINT_DEVCART_SELGAME | $4A | Nintendo Dev Card (Select flash game. A = game Nr. ([0x041048 + 96 * A] if 0x08 -> Command 0xC9)
CINT_DEVCART_NSDK | $4B | Nintendo SDK
CINT_IR_PULSE | $4C | IR pulse MOV [Y], $02 ; wait B*16 Cycles ; MOV [Y], $00

### IRQ Handling

This defines are used on macro PM_HEADER in the 3rd parameter and macros RIRQ, PRIORITY_IRQS, ENABLE_IRQS and DISABLE_IRQS. They can be combined with logic OR (character | ). Function name is the same as the definition but in lowercase.

Definition | Description
--- | ---
Individual |
IRQ_PRC_COPY | IRQ PRC Copy Complete
IRQ_PRC_DIV | IRQ PRC Frame Divider Overflow
IRQ_TMR2_HI | Timer 2 Upper-8 Overflow
IRQ_TMR2_LO | Timer 2 Lower-8 Overflow (8b only)
IRQ_TMR1_HI | Timer 1 Upper-8 Overflow
IRQ_TMR1_LO | Timer 1 Lower-8 Overflow (8b only)
IRQ_TMR3_HI | Timer 3 Upper-8 Overflow
IRQ_TMR3_PVT | Timer 3 Pivot
IRQ_32HZ | 32Hz (From 256 Hz Timer)
IRQ_8HZ | 8Hz (From 256 Hz Timer)
IRQ_2HZ | 2Hz (From 256 Hz Timer)
IRQ_1HZ | 1Hz (From 256 Hz Timer)
IRQ_IR_RX | IR Receiver
IRQ_SHOCK | Shock Sensor
IRQ_UNKNOWN | Unknown $1D
IRQ_CARTRIDGE | Cartridge IRQ
IRQ_KEY_POWER | Power Key
IRQ_KEY_RIGHT | Right Key
IRQ_KEY_LEFT | Left Key
IRQ_KEY_DOWN | Down Key
IRQ_KEY_UP | Up Key
IRQ_KEY_C | C Key
IRQ_KEY_B | B Key
IRQ_KEY_A | A Key
Combined
IRQ_PRC | INT_PRC_COPY and INT_PRC_DIV
IRQ_TMR2 | INT_TMR2_HI and INT_TMR2_LO
IRQ_TMR1 | INT_TMR1_HI and INT_TMR1_LO
IRQ_TMR3 | INT_TMR3_HI and INT_TMR3_PVT
IRQ_TMR256 | INT_32HZ, INT_8HZ, INT_2HZ and INT_1HZ
IRQ_IO | IRQ_IR_RX and IRQ_SHOCK
IRQ_KEY | INT_KEY_POWER, INT_KEY_RIGHT, INT_KEY_LEFT, INT_KEY_DOWN, INT_KEY_UP, INT_KEY_C, INT_KEY_B and INT_KEY_A
IRQ_ALL | All INT_* except IRQ_UNKNOWN and IRQ_CARTRIDGE
IRQ_TOTALLYALL | All INT_* including IRQ_UNKNOWN and IRQ_CARTRIDGE

### Header Extra Flags

This defines are used on macro PM_HEADER in the 4th parameter, they can be combined with logic OR (character | ).

Definition | Description
--- | ---
IRQF_FAR | Allow interrupt handlers to be over 32KB boundary
IRQF_NORIRQ | Don't generate RIRQ Handling (Not recommended)
IRQF_NOSTARTUP | Don't generate initialization (Not recommended)

## Example

      .include "pm_libs/pm_init.s"

      .ram variable  1
      .ram var16bits 2

      ; 1st: Game Title string, must be 12 characters
      ; 2nd: Interrupts to map, OR flags for multiple interrupts
      ; 3rd: Extra flags
      pm_header "HelloWorld  ", IRQ_KEY_POWER | IRQ_PRC_COPY, 0

      ; Power button, shutdown PM
    irq_key_power:	; Interrupt function (same name as definition but in lowercase)
      cint CINT_SHUTDOWN	; Call shutdown in BIOS

      ; PRC copy (for the example)
    irq_prc_copy:	; Interrupt function (same name as definition but in lowercase)
      mov hl, variable
      inc [hl]
      rirq IRQ_PRC_COPY

      ; Code starts here
    main:
      ; Enable power key and PRC copy interrupts
      enable_irqs IRQ_KEY_POWER | IRQ_PRC_COPY

      ; Enable interrupts
      mov f, ENABLE_IRQ

    : halt
      jmp :b

      pm_rominfo	; Optional, report ROM and RAM size

© 2011-2015 by JustBurn - Hardware documentation copy from Sublab by Team-Pokémé