Klasse PLA

java.lang.Object
libsidplay.components.pla.PLA

public final class PLA extends Object
The C64 MMU chip. This handles the coordination between the various chips in the system. The chip is thought to originate the AEC (cpu/vic select) signal, and though electrically incorrect, it is given the role of routing IRQ and NMI signals as well. In truth the IRQ and NMI signals are generated by a number of chips on the system.
Autor:
Antti Lankila
  • Felddetails

    • MAX_SIDS

      public static final int MAX_SIDS
      Maximum number of supported SIDs (mono, stereo and 3-SID)
      Siehe auch:
    • MAX_BANKS

      private static final int MAX_BANKS
      Maximum bank count (4K regions).
      Siehe auch:
    • CHAR_LENGTH

      private static final int CHAR_LENGTH
      Siehe auch:
    • BASIC_LENGTH

      private static final int BASIC_LENGTH
      Siehe auch:
    • KERNAL_LENGTH

      private static final int KERNAL_LENGTH
      Siehe auch:
    • CHAR

      private static byte[] CHAR
    • BASIC

      private static byte[] BASIC
    • KERNAL

      private static byte[] KERNAL
    • characterRomBank

      private static final Bank characterRomBank
    • basicRomBank

      private static final Bank basicRomBank
    • kernalRomBank

      private static final Bank kernalRomBank
    • customKernalRomBank

      private Bank customKernalRomBank
      Replacement of the Kernal ROM
    • sidBank

      private final PLA.SIDBank sidBank
      SID chip memory bank
    • colorRamBank

      protected final ColorRAMBank colorRamBank
    • colorRamDisconnectedBusBank

      private final Bank colorRamDisconnectedBusBank
    • ioBank

      private final PLA.IOBank ioBank
    • basic

      private boolean basic
      CPU port signals
    • kernal

      private boolean kernal
      CPU port signals
    • io

      private boolean io
      CPU port signals
    • cpuReadMap

      private final Bank[] cpuReadMap
      CPU read memory mapping in 4k chunks
    • cpuWriteMap

      private final Bank[] cpuWriteMap
      CPU write memory mapping in 4k chunks
    • vicMapPHI1

      private final Bank[] vicMapPHI1
      VIC memory bank mapping in 4k chunks
    • vicMemBase

      private int vicMemBase
      VIC memory top bits from CIA 2
    • oldBAState

      private boolean oldBAState
      BA state
    • aecDuringPhi2

      protected boolean aecDuringPhi2
      AEC state @ PHI2
    • aecDisableEvent

      private final Event aecDisableEvent
      Event to change the BA state
    • context

      private final EventScheduler context
      Event Scheduler for delayed actions
    • cpu

      private MOS6510 cpu
      Main CPU instance
    • ramBank

      private final Bank ramBank
      RAM
    • cartridge

      private Cartridge cartridge
      Connected cartridge
    • nullCartridge

      private final Cartridge nullCartridge
    • disconnectedBusBank

      protected DisconnectedBusBank disconnectedBusBank
      Disconnected data bus support
    • gamePHI1

      private boolean gamePHI1
      Cartridge GAME and EXROM signal state (active low) at PHI1 and PHI2
    • exromPHI1

      private boolean exromPHI1
      Cartridge GAME and EXROM signal state (active low) at PHI1 and PHI2
    • gamePHI2

      private boolean gamePHI2
      Cartridge GAME and EXROM signal state (active low) at PHI1 and PHI2
    • exromPHI2

      private boolean exromPHI2
      Cartridge GAME and EXROM signal state (active low) at PHI1 and PHI2
    • nmiCount

      private int nmiCount
      Number of sources asserting NMI
    • irqCount

      private int irqCount
      Number of sources asserting IRQ
    • cartridgeDma

      private boolean cartridgeDma
      Cartridge DMA
  • Konstruktordetails

    • PLA

      public PLA(EventScheduler context, Bank zeroRAMBank, Bank ramBank, byte[] charBin, byte[] basicBin, byte[] kernalBin)
  • Methodendetails

    • setCustomKernalRomBank

      public void setCustomKernalRomBank(Bank kernalRom)
      Set custom Kernal ROM.
      Parameter:
      kernalRom - custom Kernal ROM
    • reset

      public void reset()
    • setCpuPort

      public void setCpuPort(int state)
    • setGameExrom

      public void setGameExrom(boolean game, boolean exrom)
    • setGameExrom

      public void setGameExrom(boolean gamephi1, boolean exromphi1, boolean gamephi2, boolean exromphi2)
    • setBA

      public void setBA(boolean state)
      BA signal. Calls permitted during PHI1.
      Parameter:
      state - BA state.
    • setDMA

      public void setDMA(boolean state)
      Expansion port DMA signal. Calls permitted during PHI1.
      Parameter:
      state - DMA state.
    • setNMI

      public void setNMI(boolean state)
      NMI trigger signal. Calls permitted any time, but normally originated by chips at PHI1.
      Parameter:
      state - NMI state.
    • setIRQ

      public void setIRQ(boolean state)
      IRQ trigger signal. Calls permitted any time, but normally originated by chips at PHI1.
      Parameter:
      state - IRQ state.
    • updateMappingPHI2

      private void updateMappingPHI2()
    • updateMappingPHI1

      private void updateMappingPHI1()
    • cpuRead

      public byte cpuRead(int address)
      Access memory as seen by CPU
      Parameter:
      address -
      Gibt zurück:
      value at address
    • cpuWrite

      public void cpuWrite(int address, byte value)
      Access memory as seen by CPU.
      Parameter:
      address -
      value -
    • setVicMemBase

      public void setVicMemBase(int base)
      Set VIC address lines VA14 and VA15. Value for base should be one of $0000, $4000, $8000, $c000.
      Parameter:
      base -
    • getVicMemBase

      public int getVicMemBase()
    • vicReadMemoryPHI1

      public byte vicReadMemoryPHI1(int addr)
      Access memory as seen by VIC. The address should only contain the bottom 14 bits.
    • vicReadMemoryPHI2

      public byte vicReadMemoryPHI2(int addr)
      Access memory as seen by VIC. The address should only contain the bottom 14 bits. If AEC is still high (CPU is connected to the bus), the 0xff read is emulated, as the VIC has tristated itself from the bus. Otherwise, the access goes like in PHI1.
    • vicReadColorMemoryPHI2

      public byte vicReadColorMemoryPHI2(int addr)
      Access color RAM from VIC. The address should be between 0 - 0x3ff. If AEC is still high, the bottom 4 bits of the value CPU is stalled on reading will be acquired instead. These data lines are not tristated.
    • setCartridge

      public void setCartridge(Cartridge cartridge)
      Set currently connected cartridge.
      Parameter:
      cartridge -
    • isCartridge

      public boolean isCartridge()
    • setCpu

      public void setCpu(MOS6510 cpu)
    • setCia1

      public void setCia1(Bank cia1)
    • setCia2

      public void setCia2(Bank cia2)
    • setVic

      public void setVic(VIC vic)
    • getSIDBank

      public PLA.SIDBank getSIDBank()
    • getDisconnectedBusBank

      public Bank getDisconnectedBusBank()
    • getCPU

      public MOS6510 getCPU()
    • getCartridge

      public Cartridge getCartridge()