Package libsidplay.components.pla
Klasse PLA
java.lang.Object
libsidplay.components.pla.PLA
The C64 MMU chip. This handles the coordination between the various chips in
the system.
The chip is thought to originate the AEC (cpu/vic select) signal, and though
electrically incorrect, it is given the role of routing IRQ and NMI signals
as well. In truth the IRQ and NMI signals are generated by a number of chips
on the system.
- Autor:
- Antti Lankila
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Verschachtelte Klassen - Übersicht
Verschachtelte KlassenModifizierer und TypKlasseBeschreibungstatic classIO region handler. 4k region, 16 chips, 256b banks.static classSID chip memory bank maps reads and writes to the assigned SID chip -
Feldübersicht
FelderModifizierer und TypFeldBeschreibungprivate final EventEvent to change the BA stateprotected booleanAEC state @ PHI2private booleanCPU port signalsprivate static byte[]private static final intprivate static final Bankprivate CartridgeConnected cartridgeprivate booleanCartridge DMAprivate static byte[]private static final intprivate static final Bankprotected final ColorRAMBankprivate final Bankprivate final EventSchedulerEvent Scheduler for delayed actionsprivate MOS6510Main CPU instanceprivate final Bank[]CPU read memory mapping in 4k chunksprivate final Bank[]CPU write memory mapping in 4k chunksprivate BankReplacement of the Kernal ROMprotected DisconnectedBusBankDisconnected data bus supportprivate booleanCartridge GAME and EXROM signal state (active low) at PHI1 and PHI2private booleanCartridge GAME and EXROM signal state (active low) at PHI1 and PHI2private booleanCartridge GAME and EXROM signal state (active low) at PHI1 and PHI2private booleanCartridge GAME and EXROM signal state (active low) at PHI1 and PHI2private booleanCPU port signalsprivate final PLA.IOBankprivate intNumber of sources asserting IRQprivate booleanCPU port signalsprivate static byte[]private static final intprivate static final Bankprivate static final intMaximum bank count (4K regions).static final intMaximum number of supported SIDs (mono, stereo and 3-SID)private intNumber of sources asserting NMIprivate final Cartridgeprivate booleanBA stateprivate final BankRAMprivate final PLA.SIDBankSID chip memory bankprivate final Bank[]VIC memory bank mapping in 4k chunksprivate intVIC memory top bits from CIA 2 -
Konstruktorübersicht
KonstruktorenKonstruktorBeschreibungPLA(EventScheduler context, Bank zeroRAMBank, Bank ramBank, byte[] charBin, byte[] basicBin, byte[] kernalBin) -
Methodenübersicht
Modifizierer und TypMethodeBeschreibungbytecpuRead(int address) Access memory as seen by CPUvoidcpuWrite(int address, byte value) Access memory as seen by CPU.getCPU()intbooleanvoidreset()voidsetBA(boolean state) BA signal.voidsetCartridge(Cartridge cartridge) Set currently connected cartridge.voidvoidvoidvoidsetCpuPort(int state) voidsetCustomKernalRomBank(Bank kernalRom) Set custom Kernal ROM.voidsetDMA(boolean state) Expansion port DMA signal.voidsetGameExrom(boolean game, boolean exrom) voidsetGameExrom(boolean gamephi1, boolean exromphi1, boolean gamephi2, boolean exromphi2) voidsetIRQ(boolean state) IRQ trigger signal.voidsetNMI(boolean state) NMI trigger signal.voidvoidsetVicMemBase(int base) Set VIC address lines VA14 and VA15.private voidprivate voidbytevicReadColorMemoryPHI2(int addr) Access color RAM from VIC.bytevicReadMemoryPHI1(int addr) Access memory as seen by VIC.bytevicReadMemoryPHI2(int addr) Access memory as seen by VIC.
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Felddetails
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MAX_SIDS
public static final int MAX_SIDSMaximum number of supported SIDs (mono, stereo and 3-SID)- Siehe auch:
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MAX_BANKS
private static final int MAX_BANKSMaximum bank count (4K regions).- Siehe auch:
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CHAR_LENGTH
private static final int CHAR_LENGTH- Siehe auch:
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BASIC_LENGTH
private static final int BASIC_LENGTH- Siehe auch:
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KERNAL_LENGTH
private static final int KERNAL_LENGTH- Siehe auch:
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CHAR
private static byte[] CHAR -
BASIC
private static byte[] BASIC -
KERNAL
private static byte[] KERNAL -
characterRomBank
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basicRomBank
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kernalRomBank
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customKernalRomBank
Replacement of the Kernal ROM -
sidBank
SID chip memory bank -
colorRamBank
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colorRamDisconnectedBusBank
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ioBank
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basic
private boolean basicCPU port signals -
kernal
private boolean kernalCPU port signals -
io
private boolean ioCPU port signals -
cpuReadMap
CPU read memory mapping in 4k chunks -
cpuWriteMap
CPU write memory mapping in 4k chunks -
vicMapPHI1
VIC memory bank mapping in 4k chunks -
vicMemBase
private int vicMemBaseVIC memory top bits from CIA 2 -
oldBAState
private boolean oldBAStateBA state -
aecDuringPhi2
protected boolean aecDuringPhi2AEC state @ PHI2 -
aecDisableEvent
Event to change the BA state -
context
Event Scheduler for delayed actions -
cpu
Main CPU instance -
ramBank
RAM -
cartridge
Connected cartridge -
nullCartridge
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disconnectedBusBank
Disconnected data bus support -
gamePHI1
private boolean gamePHI1Cartridge GAME and EXROM signal state (active low) at PHI1 and PHI2 -
exromPHI1
private boolean exromPHI1Cartridge GAME and EXROM signal state (active low) at PHI1 and PHI2 -
gamePHI2
private boolean gamePHI2Cartridge GAME and EXROM signal state (active low) at PHI1 and PHI2 -
exromPHI2
private boolean exromPHI2Cartridge GAME and EXROM signal state (active low) at PHI1 and PHI2 -
nmiCount
private int nmiCountNumber of sources asserting NMI -
irqCount
private int irqCountNumber of sources asserting IRQ -
cartridgeDma
private boolean cartridgeDmaCartridge DMA
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Konstruktordetails
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PLA
public PLA(EventScheduler context, Bank zeroRAMBank, Bank ramBank, byte[] charBin, byte[] basicBin, byte[] kernalBin)
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Methodendetails
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setCustomKernalRomBank
Set custom Kernal ROM.- Parameter:
kernalRom- custom Kernal ROM
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reset
public void reset() -
setCpuPort
public void setCpuPort(int state) -
setGameExrom
public void setGameExrom(boolean game, boolean exrom) -
setGameExrom
public void setGameExrom(boolean gamephi1, boolean exromphi1, boolean gamephi2, boolean exromphi2) -
setBA
public void setBA(boolean state) BA signal. Calls permitted during PHI1.- Parameter:
state- BA state.
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setDMA
public void setDMA(boolean state) Expansion port DMA signal. Calls permitted during PHI1.- Parameter:
state- DMA state.
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setNMI
public void setNMI(boolean state) NMI trigger signal. Calls permitted any time, but normally originated by chips at PHI1.- Parameter:
state- NMI state.
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setIRQ
public void setIRQ(boolean state) IRQ trigger signal. Calls permitted any time, but normally originated by chips at PHI1.- Parameter:
state- IRQ state.
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updateMappingPHI2
private void updateMappingPHI2() -
updateMappingPHI1
private void updateMappingPHI1() -
cpuRead
public byte cpuRead(int address) Access memory as seen by CPU- Parameter:
address-- Gibt zurück:
- value at address
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cpuWrite
public void cpuWrite(int address, byte value) Access memory as seen by CPU.- Parameter:
address-value-
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setVicMemBase
public void setVicMemBase(int base) Set VIC address lines VA14 and VA15. Value for base should be one of $0000, $4000, $8000, $c000.- Parameter:
base-
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getVicMemBase
public int getVicMemBase() -
vicReadMemoryPHI1
public byte vicReadMemoryPHI1(int addr) Access memory as seen by VIC. The address should only contain the bottom 14 bits. -
vicReadMemoryPHI2
public byte vicReadMemoryPHI2(int addr) Access memory as seen by VIC. The address should only contain the bottom 14 bits. If AEC is still high (CPU is connected to the bus), the 0xff read is emulated, as the VIC has tristated itself from the bus. Otherwise, the access goes like in PHI1. -
vicReadColorMemoryPHI2
public byte vicReadColorMemoryPHI2(int addr) Access color RAM from VIC. The address should be between 0 - 0x3ff. If AEC is still high, the bottom 4 bits of the value CPU is stalled on reading will be acquired instead. These data lines are not tristated. -
setCartridge
Set currently connected cartridge.- Parameter:
cartridge-
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isCartridge
public boolean isCartridge() -
setCpu
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setCia1
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setCia2
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setVic
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getSIDBank
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getDisconnectedBusBank
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getCPU
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getCartridge
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