PLL_EXT + PLL_CFG[0-3] Multiplier Config (G4 Model):

0=Closed,           Multiplier 
1=Open    

00100               2x 
00110               2.5x 
01000               3x 
01110               3.5x 
01010               4x 
00111               4.5x 
01011               5x 
01001               5.5x 
01101               6x 
00101               6.5x 
00010               7x 
00001               7.5x 
01100               8x 
00110               8.5x 
10111               9x 
00111               9.5x 
11010               10x 
11000               10.5x 
11001               11x 
00000               11.5x 
11011               12x 
11111               12.5x 
10101               13x 
01110               13.5x 
11100               14x 
10001               15x 
11101               16x 
00011               PLL off/bypass (1x bus to core implied) 
01111               PLL off/0 Mhz
