Table of which opcodes have been implemented, and how much

% = 100%
 = 50%
 = 0%
* = Present, but not coded
! = Present, but suspicious of being erroneous
? = Have questions about this one, not sure how to implement it, not sure what it is etc.
 = Coded, but will likely need change
/x/ = Special flags, /M/ means Monitor Mode Only. /E/ means depends on value of exp
      /X/ means in XMP mode only, /Y/ means in Ymp mode only

*000000:  ERR: Error Exit 

0010jk: /M/ CA,Aj Ak: Sets Current Address (CA) register for channel indicated by Aj to the value specified in Ak, activates channel.

*001000: PASS: Pass instruction

*0011jk: /M/ CL,Aj, Ak: Sets Channel Limit (CL) register for channel specified by Aj to address specified by Ak.

*0012j0: /M/ CI,Aj: Clears interrupt flag and error flag for channel specified by Aj.

*0012j1: /M/ MC,Aj: Clears interrupt and error flags for channel indicated by Aj. If Aj represents an output channel, sets device master clear. If Aj represents an input channel, clears device ready-held.

%0013j0: /M/ XA Aj: Enters XA register with Aj

%0014j0: /M/ RT Sj: Enters RTC register with Sj

?0014j1: /M/ SIPI Aj: Sets interprocessor interrupt request to CPU Aj; 03 Aj3 7 on CRAY Y-MP systems. Could someone explain this better? Makes little sense to me, as it currently is

*001401: /M/ SIPI: Sets interprocessor interrupt request of CPU 0.

*001402: /M/ CIPI: Clears interprocessor interrupt

*0014j3: /M/ CLN Aj: Loads Cluster Number (CLN) register with Aj; 0< Aj < 9_(10)

%0014j4: /M/ PCI Sj: Loads Interrupt Interval (II) register with Sj

*001405: /M/ CCI: Clears Clock Interrupt

*001406:  /M/ ECI: Enables programmable clock interrupt

*001407:  /M/ DCI: Disables programmable clock interrupt

*001500:  /M/ : Clears all performance monitor counters

0015j0: /M/: Select performance Monitor

*001501: /M/: Disables Port A error correction

*001511: /M/: Disables Port B error correction

*001521: /M/: Disables Port D error correction

*001531: /M/: Enables T register data to be routed through Port D error correction, rather than Port B

*001541: /M/: Enables replacement of check byte with data on Ports C and D writes, and replacement of data with check bytes on Ports A, B, and D reads

*001551: /M/: Enables replacement of check byte with Vk data on Port C during execution of 1771jk

%00200k: VL Ak: Transmits Ak to VL

%002000: VL 1: Sets VL to 1

*002100: EFI: Enables interrupt on floating-point error

*002200: DFI: Disables interrupt on floating-point error

*002300: ERI: Enables interrupt on operand-range error

*002400: DRI: Disables interrupt on operand-range error

*002500: DBM: Disables bi-directional memory transfer

*002600: EBM: Enables bi-directional memory transfer

*002700: CMR: Completes Memory references

%0030j0: VM Sj: Transmits Sj to the VM register

%003000: VM 0: Transmits 0 to the VM register

?0034jk: SMjk 1,TS: Tests and sets semaphore jk, 0<jk37_(8. )(Bit 2^(2) of j=0.)

?0036jk: SMjk 0: Clears semaphore jk, 0<jk37_(8. )(Bit 2^(2) of j=0.)

?0037jk: SMjk 1: Sets semaphore jk, 0<jk37_(8. )(Bit 2^(2) of j=0.)

004000: EX: Normal Exit

?0050jk: J Bjk: Jumps to Bjk

?006ijkm: J exp: Jumps to exp

?007ijkm: R exp: Return jump to exp; set B00 to (P)+2.

?010ijkm: JAZ exp: Jumps to exp if A0=0

01hijkhm: /X/,/E/ Ah exp: Transmits exp to Ah (bit 2^(2) of i=1)

?011ijkm: JAN exp: Jumps to exp if A0?0

?012ijkm: JAP exp: Jumps to exp if A0 >= 0

?013ijkm: JAM exp: Jumps to exp if A0 is negative

?014ijkm: JSZ exp: Jumps to exp if S0=0

?015ijkm: JSN exp: Jumps to exp if S0?0

?016ijkm: JSP exp: Jumps to exp if S0 >= 0

?017ijkm: JSM exp: Jumps to exp if S0 is negative

?020i00nm: /E/ Ai exp: Transmits exp to Ai

020ijkm: /X/,/E/ Ai exp: Transmits exp to Ai

?021i00nm: /E/ Ai exp: Transmits ones complement of exp to Ai

021ijkm: /X/,/E/ Ai exp: Transmits ones complement of exp to Ai

021ijkm: /X/,/E/ Ai -exp: Transmits twos complement of exp to Ai

?022ijk: /E/ Ai exp: Transmits exp to Ai

%023ij0: Ai Sj: Transmits Sj to Ai

%023i01: Ai VL: Transmits VL to Ai

%024ijk: Ai Bjk: Transmits Bjk to Ai

%025ijk: Bjk Ai: Transmits Ai to Bjk

?026ij0: Ai PSj: Population count of Sj to Ai

?026ij1: Ai QSj: Population count parity of Sj to Ai

%026ij7: Ai SBj: Transmits SBj to Ai

?027ij0: Ai ZSj: Leading zero count of Sj to Ai

%027ij7: SBj Ai: Transmits Ai to SBj

%030ijk: Ai Aj + Ak: Integer sum of Aj and Ak to Ai

%030ij0: Ai Aj + 1: Integer sum of Aj and 1 to Ai

%030i0k: Ai Ak: Transmits Ak to Ai

%031ijk: Ai Aj-Ak: Integer difference of Aj less Ak to Ai

%031ij0: Ai Aj - 1: Integer difference of Aj less 1 to Ai

%031i00: Ai -1: Enters -1 into Ai

*031i0k: Ai -Ak: Transmits the negative of Ak to Ai

%032ijk: Ai Aj*Ak: Integer product of Aj and Ak to Ai

033i00: Ai CI:  Channel number of highest priority Interrupt Request to Ai

033ij0: Ai CA,Aj: Address of channel Aj to Ai (j!=0)

033ij1: Ai CE,Aj: Error flag of channel Aj to Ai (j!=0, k=1)

034ijk: Bjk,Ai ,A0: Loads Ai words from memory starting at address A0 to B registers starting at register jk

034ijk: Bjk,Ai 0,A0: Loads Ai words from memory starting at address A0 to B registers starting at register jk

035ijk: ,A0 Bjk,Ai: Stores Ai words from B registers starting at register jk to memory starting at address A0

035ijk: 0,A0 Bjk,Ai: Stores Ai words from B registers starting at register jk to memory starting at address A0

036ijk: Tjk,Ai ,A0: Loads Ai words from memory starting at address A0 to T registers starting at register jk

036ijk: Tjk,Ai 0,A0: Loads Ai words from memory starting at address A0 to T registers starting at register jk

037ijk: ,A0 Tjk,Ai: Stores Ai words from T registers starting at register jk to memory starting at address A0

037ijk: 0,A0 Tjk,Ai: Stores Ai words from T registers starting at register jk to memory starting at address A0

040i00nm: Si exp: Enters exp into Si

040ijkm: /X/ Si exp: Enters exp into Si

041i00nm: Si #exp: Enter ones complement of exp into Si

041i00nm: Si -exp: Enter twos compliment of exp into Si

041ijkm: Si #exp: Enters ones complement of exp into Si

041ijkm: Si -exp: Enters twos complement of exp into Si

042ijk: Si <exp: Forms ones mask in Si exp bits from the right; jk field gets 64 - exp

042ijk: Si #>exp: Forms zeros mask in Si exp bits from the left; jk field gets exp

%042i77: Si 1: Enters 1 into Si

%042i00: Si -1: Enters -1 into Si

%043i00: Si 0: Clears Si

043ijk: Si >exp: Forms ones mask in Si, exp bits from the left; jk field gets exp

043ijk: Si #<exp:  Forms zeros mask in Si, exp bits from the right; jk field gets 64 - exp

044ijk: Si Sj&Sk: Logical product of Sj and Sk to Si

044ij0: Si Sj&SB: Sign bit of Sj to Si, J!=0

045ijk: Si #Sk&Sj: Logical product of Sj and ones complement of Sk into Si.

045ij0: Si #SB&Sj: Sj with sign bit cleared to Si

046ijk: Si Sj\Sk: Logical difference of Sj and Sk to Si

046ij0: Si Sj\SB: Enters Sj into Si with sign bit toggled; j!=0

047ijk: Si #Sj\Sk: Logical equivalence of Sj and Sk to Si

047ij0: Si #Sj\SB: Logical equivalence of Sj and sign bit to Si; j!=0

047i0k: Si #Sk: Transmits ones complement of Sk to Si

047i00: Si #SB: Enters ones complement of sign bit into Si

050ijk: Si Sj!Si&Sk: Scalar merge of Si and Sj to Si

050ij0: Si Sj!Si&SB: Scalar merge of Si and sign bit of Sj to Si

051ijk: Si Sj!Sk: Logical sum of Sj and Sk to Si

051ij0: Si Sj!SB: Logical sum of Sj and sign bit to Si; j!=0

%051i0k: Si Sk: Transmits Sk to Si

*051i00: Si SB: Enters sign bit into Si

052ijk: S0 Si<exp: Shifts Si left exp places to S0

053ijk: Si Si>exp: Shifts Si right exp places to S0

054ijk: Si Si<exp: Shifts Si left exp places to Si

055ijk: Si Si>exp: Shifts Si right exp places to Si

056ijk: Si Si,Sj<Ak: Shifts Si and Sj left Ak places to Si

056ij0: Si Si,Sj<0: Shifts Si and Sj left one place to Si

056i0k: Si Si<Ak: Shifts Si left Ak places to Si

057ijk: Si Sj,Si>Ak: Shifts Sj and Si right Ak places to Si

057ij0: Si Sj,Si>1:  Shifts Sj and Si right one place to Si

057i0k: Si Si>Ak: Shifts Si right Ak places to Si

%060ijk: Si Sj+Sk: Integer sum of Sj and Sk to Si

060ij0: Si Sj+S0: Integer sum of Sj and the sign bit to Si

%061ijk: Si Sj-Sk: Integer difference of Sj less Sk to Si

*061ij0: Si Sj-S0: Integer difference of Sj less the sign bit to Si

*061i0k: Si -Sk: Transmits negative of Sk to Si

062ijk: Si Sj+FSk: Floating-point sum of Sj and Sk to Si

062i0k: Si +FSk: Normalizes Sk to Si

063ijk: Si Sj-FSk: Floating-point difference of Sj less Sk to Si

063i0k: Si -FSk: Transmits the negative of Sk as a normalized floating-point value to Si

064ijk: Si Sj*FSk: Floating-point product of Sj and Sk to Si

065ijk: Si Sj*HSk: Half-precision, rounded, floating-point product of Si and Sk to Si

066ijk: Si Sj*RSk: Rounded, floating-point product of Sj and Sk to Si

067ijk: Si Sj*ISk: 2 minus floating-point product of Sj and Sk to Si

070ij0: Si /HSj: Floating-point reciprocal approximation of Sj to Si

070i0k: Si Ak: Transmits Ak to Si with no sign extension

071i1k: Si +Ak: Transmits Ak to Si with sign extension

071i2k: Si +FAk: Transmits Ak to Si as an unnormalized floating-point value

071i30: Si 0.6: Transmits 0.75*(2^(48)) to Si as a normalized floating-point constant

*071i40: Si 0.4: Transmits 0.5 to Si as a normalized floating-point constant

%071i50: Si 1.: Transmits 1.0 to Si as a normalized floating-point constant

%071i60: Si 2.: Transmits 2.0 to Si as a normalized floating-point constant

%071i70: Si 4.: Transmits 2.0 to Si as a normalized floating-point constant

%072i00: Si RT: Transmits (RTC) to Si

072i02: Si SM: Transmits semaphores to Si

%072ij3: Si STj: Transmits STj register to Si

%073i00: Si VM: Transmits VM to Si

073i02: SM Si: Loads semaphores from Si

%073i01: Si SR0: Transmits SR0 to Si

*073i05: SR0 Si: Transmits Si bits 2^(48) through 2^(52) to SR0

073i21: /M/ Si SR2: Reads PM counters 00 through 17 and increment pointer. If in Y-mode, increments performance counter

073i31: /M/ Si SR3: Reads PM counters 20 through 37 and increment pointer. If in Y-mode, clears all maintenance modes

%074ijk: Si Tjk: Transmits Tjk to Si

%075ijk: Tjk Si: Transmits Si to Tjk

076ijk: Si Vj,Ak: Transmits (Vj, element Ak) to Si

077ijk: Vi,Ak Sj: Transmits Sj to Vi element Ak

077i0k: Vi,Ak 0: Clears element Ak of register Vi

100i00nm: Ai exp,0: Loads from exp to Ai

100ijkm: /X/ Ai exp,0: Loads from exp to Ai

100ijkm: /X/ Ai exp,: Loads from exp to Ai

10hi000: Ai ,Ah: Loads from Ah to Ai

10hijkm: /X/ Ai exp,Ah: Loads from (Ah+exp) to Ai; Ahp0

10hi0000: /X/ Ai ,Ah: Loads from Ah to Ai

10hi00nm: /Y/ Ai exp,Ai: Loads Ai from (Ah+exp)

11hi00nm: exp,Ah Ai: Stores Ai to Ah+exp; Ahp0

110i00nm: exp,0 Ai: Stores Ai to exp

110ijkm: /X/ exp,0 Ai: Stores Ai to exp

11hi0000: ,Ah Ai: Stores Ai to Ah

11hijkm: /X/ exp,Ah Ai: Stores Ai to Ah+exp; Ahp0

12hi00nm: Si Ah,exp: Loads from (Ah+exp) to Si; Ahp0

120i00nm: Si exp,0: Loads from exp to Si

12hi0000: Si ,Ah: Loads from Ah to Si

12hijkm: /X/ Si exp,Ah: Loads from (Ah+exp) to Si; Ahp0

13hi00nm: exp,Ah Si: Stores Si to Ah+exp; Ahp0

130i00nm: exp,0 Si: Stores Si to exp

13hi0000: ,Ah Si: Stores Si to Ah

13hijkm: /X/ exp,Ah Si: Stores Si to Ah+exp; Ahp0

140ijk: Vi Sj&Vk: Logical products of Sj and Vk to Vi

141ijk: Vi Vj&Vk: Logical products of Vj and Vk to Vi

142ijk: Vi Sj!Vk: Logical sums of Sj and Vk to Vi

142i0k: Vi Vk: Transmits Vk to Vi

143ijk: Vi Vj!Vk: Logical sums of Vj and Vk to Vi

144ijk: Vi Sj\Vk: Logical differences of Sj and Vk to Vi

145ijk: Vi Vj\Vk: Logical differences of Vj and Vk to Vi

145iii: Vi 0: Clears Vi

146ijk: Vi Sj!Vk&VM: Vector merge of Sj and Vk to Vi

146i0k: Vi #VM&Vk: Vector merge of Vk and zero to Vi

147ijk: Vi Vj!Vk&VM: Vector merge of Vj and Vk to Vi

150ijk: Vj<Ak: Shifts Vj left Ak places to Vi

150ij0: Vi Vj<1: Shifts Vj left one place to Vi

151ijk: Vi Vj>Ak: Shifts Vj right Ak places to Vi

151ij0: Vi Vj>1: Shifts Vj right one place to Vi

152ijk: Vi Vj,Vj<Ak: Double-shifts Vj left Ak places to Vi

152ij0: Vi Vj,Vj<1: Double-shifts Vj left one place to Vi

153ijk: Vi Vj,Vj>Ak: Double-shifts Vj right Ak places to Vi

153ij0: Vi Vj,Vj>1: Double-shifts Vj right one place to Vi

154ijk: Vi Sj+Vk: Integer sums of Sj and Vk to Vi

155ijk: Vi Vj+Vk: Integer sums of Vj and Vk to Vi

156ijk: Vi Sj-Vk: Integer differences of Sj and Vk to Vi

156i0k: Vi -Vk: Transmits twos complement of Vk to Vi

157ijk: Vi Vj-Vk: Integer differences of Vj less Vk to Vi

160ijk: Vi Sj*FVk: Floating-point products of Sj and Vk to Vi

161ijk: Vi Vj*FVk: Floating-point products of Vj and Vk to Vi

162ijk: Vi Sj*HVk: Half-precision, rounded, floating-point products of Sj and Vk to Vi

163ijk: Vi Vj*HVk: Half-precision, rounded, floating-point products of Vj and Vk to Vi

164ijk: Vi Sj*RVk: Rounded floating-point products of Sj and Vk to Vi

165ijk: Vi Vj*RVk: Rounded floating-point products of Vj and Vk to Vi

166ijk: Vi Sj*Vk: 32-bit integer product of Sj and Vk to Vi

166ijk: /X/ Vi Sj*IVk: Two minus floating-point products of Sj and Vk to Vi

167ijk: Vi Vj*Ivk: Two minus floating-point products of Vj and Vk to Vi

170ijk: Vi Sj+FVk: Floating-point sums of Sj and Vk to Vi

170i0k: Vi +FVk: Normalizes Vk to Vi

171ijk: Vi Vj+FVk: Floating-point sums of Vj and Vk to Vi

172ijk: Vi Sj-FVk: Floating-point differences of Sj less Vk to Vi

172i0k: Vi -FVk: Transmits normalized negative of Vk to Vi

173ijk: Vi Vj-FVk: Floating-point differences of Vj less Vk to Vi

174ij0: Vi /HVj: Floating-point reciprocal approximations of Vj to Vi

174ij1: Vi PVj: Population count of Vj to Vi

174ij2: Vi QVj: Population count parities of Vj to Vi

1750j0: VM Vj,Z: Sets VM bits for zero elements of Vj

1750j1: VM Vj,N: Sets VM bits for nonzero elements of Vj

1750j2: VM Vj,P: Sets VM bits for positive elements of Vj

1750j3: VM Vj,M: Sets VM bits for negative elements of Vj

1750j4: Vi,VM Vj,Z: Sets VM bits for zero elements of Vj, and register Vi to the compressed indices of Vj for zero elements of Vj

1750j5: Vi,VM Vj,N: Sets VM bits for nonzero elements of Vj, and register Vi to the compressed indices of Vj for nonzero elements of Vj

1750j6: Vi,VM Vj,P: Sets VM bits for positive elements of Vj, and register Vi to the compressed indices of Vj for positive elements of Vj

1750j7: Vi,VM Vj,M: Sets VM bits for negative elements of Vj, and register Vi to the compressed indices of Vj for negative elements of Vj

176i0k: Vi ,A0,Ak: Loads VL words from memory starting at A0 incrementing by Ak and load into Vi

176i00: Vi ,A0,1: Loads VL words from consecutive memory addresses starting with A0 and load into Vi

176i1k: Vi ,A0,Vk: Reads VL words to Vi from (A0 + Vk)

1770jk: ,A0,Ak Vk: Stores VL words from Vj to memory starting at A0 incrementing by Ak

1770j0: ,A0,1 Vj: Stores Vj to memory in consecutive addresses starting with A0

1771jk: ,A0,Vk Vj: Stores VL words from Vj to (A0 + Vk)
