cpldfit: version K.34 Xilinx Inc.
Fitter Report
Design Name: X9572_zxmmc2 Date: 1-11-2009, 10:51PM
Device Used: XC9572XL-5-VQ64
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
67 /72 ( 93%) 274 /360 ( 76%) 161/216 ( 75%) 48 /72 ( 67%) 52 /52 (100%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 16/18 48/54 75/90 7/13
FB2 16/18 46/54 81/90 10/13
FB3 17/18 19/54 50/90 2/14
FB4 18/18* 48/54 68/90 6/12
----- ----- ----- -----
67/72 161/216 274/360 25/52
* - Resource is exhausted
** Global Control Resources **
Signal 'clock' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 26 26 | I/O : 46 46
Output : 15 15 | GCK/IO : 3 3
Bidirectional : 10 10 | GTS/IO : 2 2
GCK : 1 1 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 52 52
** Power Data **
There are 67 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
INFO:Cpld - Inferring BUFG constraint for signal 'clock' based upon the LOC
constraint 'P16'. It is recommended that you declare this BUFG explicitedly
in your design. Note that for certain device families the output of a BUFG
constraint can not drive a gated clock, and the BUFG constraint will be
ignored.
INFO:Cpld - Inferring BUFG constraint for signal 'z80_databus<2>' based upon the
LOC constraint 'P17'. It is recommended that you declare this BUFG
explicitedly in your design. Note that for certain device families the output
of a BUFG constraint can not drive a gated clock, and the BUFG constraint
will be ignored.
INFO:Cpld - Inferring BUFG constraint for signal 'z80_databus<3>' based upon the
LOC constraint 'P15'. It is recommended that you declare this BUFG
explicitedly in your design. Note that for certain device families the output
of a BUFG constraint can not drive a gated clock, and the BUFG constraint
will be ignored.
WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'N6' is
ignored. Most likely the signal is gated and therefore cannot be used as a
global control signal.
WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'N7' is
ignored. Most likely the signal is gated and therefore cannot be used as a
global control signal.
************************* Summary of Mapped Logic ************************
** 25 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
memory_bank<1> 3 14 FB1_2 8 I/O O STD FAST RESET
z80_databus<4> 4 15 FB1_4 13 I/O I/O STD FAST
z80_databus<3> 14 16 FB1_9 15 GCK/I/O I/O STD FAST
z80_databus<1> 4 15 FB1_10 18 I/O I/O STD FAST
z80_databus<2> 4 15 FB1_14 17 GCK/I/O I/O STD FAST
z80_databus<0> 14 16 FB1_15 19 I/O I/O STD FAST
ram_cs 2 9 FB1_17 20 I/O O STD FAST
z80_databus<7> 13 15 FB2_2 60 I/O I/O STD FAST
memory_bank<3> 4 15 FB2_3 58 I/O I/O STD FAST RESET
z80_databus<6> 3 13 FB2_4 59 I/O I/O STD FAST
rom_cs 2 9 FB2_5 61 I/O O STD FAST
memory_bank<4> 4 15 FB2_9 64 GSR/I/O I/O STD FAST RESET
spi_clock 2 2 FB2_11 2 GTS/I/O O STD FAST RESET
OUT1_reg<1> 8 19 FB2_12 4 I/O O STD FAST RESET
spi_dataout 4 18 FB2_14 5 GTS/I/O O STD FAST RESET
OUT1_reg<0> 8 19 FB2_15 6 I/O O STD FAST RESET
memory_bank<2> 3 14 FB2_17 7 I/O O STD FAST RESET
edge_romcs 2 4 FB3_9 27 I/O O STD FAST
z80_wait 1 2 FB3_17 38 I/O O STD FAST
z80_nmi 1 2 FB4_2 43 I/O O STD FAST
memory_bank<0> 6 19 FB4_6 49 I/O O STD FAST RESET
cts_out 3 14 FB4_8 45 I/O O STD FAST RESET
net_out 1 2 FB4_11 48 I/O O STD FAST
z80_databus<5> 3 13 FB4_14 50 I/O I/O STD FAST
rs_232out 1 2 FB4_15 56 I/O O STD FAST
** 42 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
bus_cnt<0> 2 4 FB1_1 STD RESET
wait_cnt<1> 3 16 FB1_3 STD RESET
data_out 3 14 FB1_5 STD RESET
comms_data 3 14 FB1_6 STD RESET
bus_cnt<1> 3 5 FB1_7 STD RESET
wait_cnt<0> 4 16 FB1_11 STD RESET
fastpage<1> 4 16 FB1_12 STD RESET
fastpage<0> 4 16 FB1_13 STD RESET
$OpTx$FX_DC$41 4 7 FB1_18 STD
nmi_enable 9 19 FB2_6 STD RESET
spi_tx<0> 6 18 FB2_7 STD RESET
spi_tx<1> 5 18 FB2_8 STD RESET
spi_tx<2> 4 18 FB2_10 STD RESET
flashwrite 3 17 FB2_13 STD RESET
spi_tx<3> 3 18 FB2_16 STD RESET
$OpTx$$OpTx$FX_DC$40_INV$431 1 3 FB3_2 STD
rx_register<7> 2 6 FB3_3 STD RESET
rx_register<6> 2 6 FB3_4 STD RESET
rx_register<5> 2 6 FB3_5 STD RESET
rx_register<4> 2 6 FB3_6 STD RESET
rx_register<3> 2 6 FB3_7 STD RESET
rx_register<2> 2 6 FB3_8 STD RESET
rx_register<1> 2 6 FB3_10 STD RESET
rx_register<0> 2 6 FB3_11 STD RESET
shift<6> 5 7 FB3_12 STD RESET
shift<5> 5 7 FB3_13 STD RESET
shift<4> 5 7 FB3_14 STD RESET
shift<3> 5 7 FB3_15 STD RESET
shift<2> 5 7 FB3_16 STD RESET
shift<1> 5 7 FB3_18 STD RESET
$OpTx$FX_SC$45 2 17 FB4_1 STD
fastpage<2> 3 14 FB4_3 STD RESET
tx_register<0> 4 18 FB4_4 STD RESET
$OpTx$$OpTx$FX_DC$42_INV$432 4 17 FB4_5 STD
tx_register<7> 5 10 FB4_7 STD RESET
tx_register<6> 5 10 FB4_9 STD RESET
tx_register<5> 5 10 FB4_10 STD RESET
tx_register<4> 5 10 FB4_12 STD RESET
tx_register<3> 5 10 FB4_13 STD RESET
tx_register<2> 5 10 FB4_16 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
tx_register<1> 5 10 FB4_17 STD RESET
shift<0> 5 7 FB4_18 STD RESET
** 27 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
address<3> FB1_3 12 I/O I
address<4> FB1_5 9 I/O I
z80_wr FB1_6 10 I/O I
z80_rd FB1_8 11 I/O I
clock FB1_11 16 GCK/I/O GCK
address<5> FB1_12 23 I/O I
address<1> FB2_6 62 I/O I
address<0> FB2_8 63 I/O I
spi_datain FB2_10 1 I/O I
address<7> FB3_2 22 I/O I
z80_mreq FB3_3 31 I/O I
reset FB3_4 32 I/O I
z80_iorq FB3_5 24 I/O I
hi_address<0> FB3_6 34 I/O I
address<6> FB3_8 25 I/O I
kempston<2> FB3_10 39 I/O I
hi_address<1> FB3_11 33 I/O I
ramrom FB3_12 40 I/O I
kempston<0> FB3_14 35 I/O I
kempston<1> FB3_15 36 I/O I
net_in FB3_16 42 I/O I
dtr_in FB4_3 46 I/O I
residos FB4_4 47 I/O I
rs_232in FB4_5 44 I/O I
kempston_enable FB4_10 51 I/O I
if1_enable FB4_12 52 I/O I
address<2> FB4_17 57 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X - Signal used as input to the macrocell logic.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 48/6
Number of signals used by logic mapping into function block: 48
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
bus_cnt<0> 2 0 0 3 FB1_1 (b) (b)
memory_bank<1> 3 0 0 2 FB1_2 8 I/O O
wait_cnt<1> 3 0 0 2 FB1_3 12 I/O I
z80_databus<4> 4 0 0 1 FB1_4 13 I/O I/O
data_out 3 0 0 2 FB1_5 9 I/O I
comms_data 3 0 0 2 FB1_6 10 I/O I
bus_cnt<1> 3 0 \/2 0 FB1_7 (b) (b)
(unused) 0 0 \/5 0 FB1_8 11 I/O I
z80_databus<3> 14 9<- 0 0 FB1_9 15 GCK/I/O I/O
z80_databus<1> 4 1<- /\2 0 FB1_10 18 I/O I/O
wait_cnt<0> 4 0 /\1 0 FB1_11 16 GCK/I/O GCK
fastpage<1> 4 0 0 1 FB1_12 23 I/O I
fastpage<0> 4 0 0 1 FB1_13 (b) (b)
z80_databus<2> 4 0 \/1 0 FB1_14 17 GCK/I/O I/O
z80_databus<0> 14 9<- 0 0 FB1_15 19 I/O I/O
(unused) 0 0 /\5 0 FB1_16 (b) (b)
ram_cs 2 0 /\3 0 FB1_17 20 I/O O
$OpTx$FX_DC$41 4 0 0 1 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$FX_DC$41 17: bus_cnt<1> 33: memory_bank<4>
2: memory_bank<4>.PIN 18: dtr_in 34: net_in
3: memory_bank<3>.PIN 19: fastpage<0> 35: ramrom
4: z80_databus<6>.PIN 20: fastpage<1> 36: reset
5: z80_databus<5>.PIN 21: fastpage<2> 37: residos
6: z80_databus<1>.PIN 22: hi_address<0> 38: rx_register<0>
7: z80_databus<0>.PIN 23: hi_address<1> 39: rx_register<1>
8: address<0> 24: if1_enable 40: rx_register<2>
9: address<1> 25: kempston<0> 41: rx_register<3>
10: address<2> 26: kempston<1> 42: rx_register<4>
11: address<3> 27: kempston<2> 43: wait_cnt<0>
12: address<4> 28: kempston_enable 44: wait_cnt<1>
13: address<5> 29: memory_bank<0> 45: z80_iorq
14: address<6> 30: memory_bank<1> 46: z80_mreq
15: address<7> 31: memory_bank<2> 47: z80_rd
16: bus_cnt<0> 32: memory_bank<3> 48: z80_wr
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
bus_cnt<0> ...............X...................X........X..X.. 4
memory_bank<1> .....X.XXXXXXXXXX..................X........X..X.. 14
wait_cnt<1> ....X..XXXXXXXX........X.........X.X......XXX..X.. 16
z80_databus<4> X.X....XXXXXXXX............X....X........X..X.X... 15
data_out ......XXXXXXXXXXX..................X........X..X.. 14
comms_data ......XXXXXXXXXXX..................X........X..X.. 14
bus_cnt<1> ...............XX..................X........X..X.. 5
z80_databus<3> XX.....XXXXXXXX..X.........X...X........X...X.X... 16
z80_databus<1> X......XXXXXXXX..........X.X.X........X.....X.X... 15
wait_cnt<0> ....X..XXXXXXXX........X.........X.X......XXX..X.. 16
fastpage<1> ...X...XXXXXXXXXX..X...............XX.......X..X.. 16
fastpage<0> ....X..XXXXXXXXXX.X...............XX........X..X.. 16
z80_databus<2> X......XXXXXXXX...........XX..X........X....X.X... 15
z80_databus<0> X......XXXXXXXX.........X..XX....X...X......X.X... 16
ram_cs ..................XXXXX............X.........XXX.. 9
$OpTx$FX_DC$41 ..........XXXXX........X...X...................... 7
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 46/8
Number of signals used by logic mapping into function block: 46
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 \/5 0 FB2_1 (b) (b)
z80_databus<7> 13 8<- 0 0 FB2_2 60 I/O I/O
memory_bank<3> 4 0 /\1 0 FB2_3 58 I/O I/O
z80_databus<6> 3 0 \/1 1 FB2_4 59 I/O I/O
rom_cs 2 1<- \/4 0 FB2_5 61 I/O O
nmi_enable 9 4<- 0 0 FB2_6 62 I/O I
spi_tx<0> 6 1<- 0 0 FB2_7 (b) (b)
spi_tx<1> 5 1<- /\1 0 FB2_8 63 I/O I
memory_bank<4> 4 0 /\1 0 FB2_9 64 GSR/I/O I/O
spi_tx<2> 4 0 0 1 FB2_10 1 I/O I
spi_clock 2 0 \/2 1 FB2_11 2 GTS/I/O O
OUT1_reg<1> 8 3<- 0 0 FB2_12 4 I/O O
flashwrite 3 0 /\1 1 FB2_13 (b) (b)
spi_dataout 4 0 \/1 0 FB2_14 5 GTS/I/O O
OUT1_reg<0> 8 3<- 0 0 FB2_15 6 I/O O
spi_tx<3> 3 0 /\2 0 FB2_16 (b) (b)
memory_bank<2> 3 0 0 2 FB2_17 7 I/O O
(unused) 0 0 \/2 3 FB2_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$40_INV$431 17: address<2> 32: nmi_enable
2: $OpTx$$OpTx$FX_DC$42_INV$432 18: address<3> 33: reset
3: $OpTx$FX_DC$41 19: address<4> 34: rs_232in
4: $OpTx$FX_SC$45 20: address<5> 35: rx_register<6>
5: z80_databus<7>.PIN 21: address<6> 36: rx_register<7>
6: z80_databus<6>.PIN 22: address<7> 37: spi_dataout
7: z80_databus<5>.PIN 23: bus_cnt<0> 38: spi_tx<0>
8: z80_databus<4>.PIN 24: bus_cnt<1> 39: spi_tx<1>
9: z80_databus<3>.PIN 25: fastpage<0> 40: spi_tx<2>
10: z80_databus<2>.PIN 26: fastpage<1> 41: spi_tx<3>
11: z80_databus<1>.PIN 27: fastpage<2> 42: tx_register<7>
12: z80_databus<0>.PIN 28: flashwrite 43: z80_iorq
13: OUT1_reg<0> 29: hi_address<0> 44: z80_mreq
14: OUT1_reg<1> 30: hi_address<1> 45: z80_rd
15: address<0> 31: kempston_enable 46: z80_wr
16: address<1>
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
z80_databus<7> ..X...........XXXXXXXX....X...X..X.X......X.X..... 15
memory_bank<3> ........X.....XXXXXXXXXX........X.........XX.X.... 15
z80_databus<6> ..X...........XXXXXXXX...X........X.......X.X..... 13
rom_cs ........................XX.XXX..X..........XXX.... 9
nmi_enable ....XXXXX.....XXXXXXXXXX.......XX.........X..X.... 19
spi_tx<0> ..............XXXXXXXXXX........X....XXXX.X.XX.... 18
spi_tx<1> ..............XXXXXXXXXX........X....XXXX.X.XX.... 18
memory_bank<4> .......X......XXXXXXXXXX........X.........XX.X.... 15
spi_tx<2> ..............XXXXXXXXXX........X....XXXX.X.XX.... 18
spi_clock ................................X....X............ 2
OUT1_reg<1> ....XXXX..X..XXXXXXXXXXX........X.........X..X.... 19
flashwrite ....XXXX......XXXXXXXXXX........X.........X..X.... 17
spi_dataout XX.XX.........XXXXXXXX..........X...XX...XX.X..... 18
OUT1_reg<0> ....XXXX...XX.XXXXXXXXXX........X.........X..X.... 19
spi_tx<3> ..............XXXXXXXXXX........X....XXXX.X.XX.... 18
memory_bank<2> .........X....XXXXXXXXXX........X.........X..X.... 14
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 19/35
Number of signals used by logic mapping into function block: 19
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB3_1 (b)
$OpTx$$OpTx$FX_DC$40_INV$431
1 0 0 4 FB3_2 22 I/O I
rx_register<7> 2 0 0 3 FB3_3 31 I/O I
rx_register<6> 2 0 0 3 FB3_4 32 I/O I
rx_register<5> 2 0 0 3 FB3_5 24 I/O I
rx_register<4> 2 0 0 3 FB3_6 34 I/O I
rx_register<3> 2 0 0 3 FB3_7 (b) (b)
rx_register<2> 2 0 0 3 FB3_8 25 I/O I
edge_romcs 2 0 0 3 FB3_9 27 I/O O
rx_register<1> 2 0 0 3 FB3_10 39 I/O I
rx_register<0> 2 0 0 3 FB3_11 33 I/O I
shift<6> 5 0 0 0 FB3_12 40 I/O I
shift<5> 5 0 0 0 FB3_13 (b) (b)
shift<4> 5 0 0 0 FB3_14 35 I/O I
shift<3> 5 0 0 0 FB3_15 36 I/O I
shift<2> 5 0 0 0 FB3_16 42 I/O I
z80_wait 1 0 0 4 FB3_17 38 I/O O
shift<1> 5 0 0 0 FB3_18 (b) (b)
Signals Used by Logic in Function Block
1: fastpage<1> 8: shift<3> 14: spi_tx<1>
2: fastpage<2> 9: shift<4> 15: spi_tx<2>
3: flashwrite 10: shift<5> 16: spi_tx<3>
4: reset 11: shift<6> 17: wait_cnt<0>
5: shift<0> 12: spi_datain 18: wait_cnt<1>
6: shift<1> 13: spi_tx<0> 19: z80_rd
7: shift<2>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
$OpTx$$OpTx$FX_DC$40_INV$431
.............XXX........................ 3
rx_register<7> ...X......X.XXXX........................ 6
rx_register<6> ...X.....X..XXXX........................ 6
rx_register<5> ...X....X...XXXX........................ 6
rx_register<4> ...X...X....XXXX........................ 6
rx_register<3> ...X..X.....XXXX........................ 6
rx_register<2> ...X.X......XXXX........................ 6
edge_romcs XXX...............X..................... 4
rx_register<1> ...XX.......XXXX........................ 6
rx_register<0> ...X.......XXXXX........................ 6
shift<6> ...X.....XX.XXXX........................ 7
shift<5> ...X....XX..XXXX........................ 7
shift<4> ...X...XX...XXXX........................ 7
shift<3> ...X..XX....XXXX........................ 7
shift<2> ...X.XX.....XXXX........................ 7
z80_wait ................XX...................... 2
shift<1> ...XXX......XXXX........................ 7
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 48/6
Number of signals used by logic mapping into function block: 48
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
$OpTx$FX_SC$45 2 0 0 3 FB4_1 (b) (b)
z80_nmi 1 0 0 4 FB4_2 43 I/O O
fastpage<2> 3 0 0 2 FB4_3 46 I/O I
tx_register<0> 4 0 0 1 FB4_4 47 I/O I
$OpTx$$OpTx$FX_DC$42_INV$432
4 0 \/1 0 FB4_5 44 I/O I
memory_bank<0> 6 1<- 0 0 FB4_6 49 I/O O
tx_register<7> 5 0 0 0 FB4_7 (b) (b)
cts_out 3 0 0 2 FB4_8 45 I/O O
tx_register<6> 5 0 0 0 FB4_9 (b) (b)
tx_register<5> 5 0 0 0 FB4_10 51 I/O I
net_out 1 0 0 4 FB4_11 48 I/O O
tx_register<4> 5 0 0 0 FB4_12 52 I/O I
tx_register<3> 5 0 0 0 FB4_13 (b) (b)
z80_databus<5> 3 0 0 2 FB4_14 50 I/O I/O
rs_232out 1 0 0 4 FB4_15 56 I/O O
tx_register<2> 5 0 0 0 FB4_16 (b) (b)
tx_register<1> 5 0 0 0 FB4_17 57 I/O I
shift<0> 5 0 0 0 FB4_18 (b) (b)
Signals Used by Logic in Function Block
1: $OpTx$$OpTx$FX_DC$42_INV$432 17: address<5> 33: spi_datain
2: $OpTx$FX_DC$41 18: address<6> 34: spi_tx<0>
3: $OpTx$FX_SC$45 19: address<7> 35: spi_tx<1>
4: z80_databus<7>.PIN 20: bus_cnt<0> 36: spi_tx<2>
5: z80_databus<6>.PIN 21: bus_cnt<1> 37: spi_tx<3>
6: z80_databus<5>.PIN 22: comms_data 38: tx_register<0>
7: z80_databus<4>.PIN 23: data_out 39: tx_register<1>
8: z80_databus<3>.PIN 24: fastpage<0> 40: tx_register<2>
9: z80_databus<2>.PIN 25: hi_address<0> 41: tx_register<3>
10: z80_databus<1>.PIN 26: hi_address<1> 42: tx_register<4>
11: z80_databus<0>.PIN 27: memory_bank<0> 43: tx_register<5>
12: address<0> 28: nmi_enable 44: tx_register<6>
13: address<1> 29: reset 45: tx_register<7>
14: address<2> 30: rs_232in 46: z80_iorq
15: address<3> 31: rx_register<5> 47: z80_rd
16: address<4> 32: shift<0> 48: z80_wr
Signal 1 2 3 4 5 FB
Name 0----+----0----+----0----+----0----+----0----+----0 Inputs
$OpTx$FX_SC$45 ...........XXXXXXXXXX.......X....XXXX........X.X.. 17
z80_nmi ...........................X.X.................... 2
fastpage<2> ...X.......XXXXXXXXXX.......X................X.X.. 14
tx_register<0> ...........XXXXXXXXXX.......X....XXXXX.......X.X.. 18
$OpTx$$OpTx$FX_DC$42_INV$432
...........XXXXXXXXXX.......X....XXXX........X.X.. 17
memory_bank<0> ......X...XXXXXXXXXXX..XXXX.X................X.X.. 19
tx_register<7> X.X.X.......................X....XXXX......XX..... 10
cts_out ......X....XXXXXXXXXX.......X................X.X.. 14
tx_register<6> X.X..X......................X....XXXX.....XX...... 10
tx_register<5> X.X...X.....................X....XXXX....XX....... 10
net_out .....................XX........................... 2
tx_register<4> X.X....X....................X....XXXX...XX........ 10
tx_register<3> X.X.....X...................X....XXXX..XX......... 10
z80_databus<5> .X.........XXXXXXXX....X......X..............XX... 13
rs_232out .....................XX........................... 2
tx_register<2> X.X......X..................X....XXXX.XX.......... 10
tx_register<1> X.X.......X.................X....XXXXXX........... 10
shift<0> ............................X..XXXXXX............. 7
0----+----1----+----2----+----3----+----4----+----5
0 0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
$OpTx$$OpTx$FX_DC$40_INV$431 <= (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3));
$OpTx$$OpTx$FX_DC$42_INV$432 <= ((reset AND NOT spi_tx(0) AND spi_tx(1))
OR (reset AND NOT spi_tx(0) AND spi_tx(2))
OR (reset AND NOT spi_tx(0) AND spi_tx(3))
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND
NOT z80_wr));
$OpTx$FX_DC$41 <= ((NOT address(7) AND address(5) AND address(3) AND
address(4))
OR (NOT address(7) AND NOT address(6) AND address(3) AND
address(4) AND NOT kempston_enable)
OR (address(7) AND address(6) AND address(5) AND
address(3) AND NOT address(4) AND NOT if1_enable)
OR (address(7) AND address(6) AND address(5) AND
NOT address(3) AND address(4) AND NOT if1_enable));
$OpTx$FX_SC$45 <= ((NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_iorq AND spi_tx(0) AND bus_cnt(0) AND
NOT bus_cnt(1) AND NOT z80_wr)
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_iorq AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3) AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr));
FTCPE_OUT1_reg0: FTCPE port map (OUT1_reg(0),OUT1_reg_T(0),clock,'0','0');
OUT1_reg_T(0) <= ((spi_dataout_OBUF.EXP)
OR (spi_tx(3).EXP)
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND z80_databus(4).PIN AND NOT z80_iorq AND
NOT z80_databus(0).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(0))
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_iorq AND NOT z80_databus(7).PIN AND
NOT z80_databus(0).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(0))
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_iorq AND z80_databus(0).PIN AND
NOT z80_databus(5).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND NOT OUT1_reg(0))
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_iorq AND NOT z80_databus(0).PIN AND
NOT z80_databus(5).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(0))
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_iorq AND NOT z80_databus(0).PIN AND
bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(0) AND
z80_databus(6).PIN));
FTCPE_OUT1_reg1: FTCPE port map (OUT1_reg(1),OUT1_reg_T(1),clock,'0','0');
OUT1_reg_T(1) <= ((spi_clock_OBUF.EXP)
OR (flashwrite.EXP)
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND z80_databus(4).PIN AND NOT z80_databus(1).PIN AND
NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(1))
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND z80_databus(1).PIN AND NOT z80_iorq AND
NOT z80_databus(5).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND NOT OUT1_reg(1))
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_databus(1).PIN AND NOT z80_iorq AND
NOT z80_databus(7).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(1))
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_databus(1).PIN AND NOT z80_iorq AND
NOT z80_databus(5).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(1))
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_databus(1).PIN AND NOT z80_iorq AND
bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(1) AND
z80_databus(6).PIN));
FDCPE_bus_cnt0: FDCPE port map (bus_cnt(0),bus_cnt_D(0),clock,'0','0',reset);
bus_cnt_D(0) <= (NOT z80_iorq AND NOT bus_cnt(0) AND NOT z80_wr);
FDCPE_bus_cnt1: FDCPE port map (bus_cnt(1),bus_cnt_D(1),clock,'0','0',reset);
bus_cnt_D(1) <= ((NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr)
OR (NOT z80_iorq AND NOT bus_cnt(0) AND bus_cnt(1) AND NOT z80_wr));
FDCPE_comms_data: FDCPE port map (comms_data,z80_databus(0).PIN,clock,NOT reset,'0',comms_data_CE);
comms_data_CE <= (address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
NOT address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);
FDCPE_cts_out: FDCPE port map (cts_out,NOT z80_databus(4).PIN,clock,'0',NOT reset,cts_out_CE);
cts_out_CE <= (address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
NOT address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);
FDCPE_data_out: FDCPE port map (data_out,z80_databus(0).PIN,clock,'0',NOT reset,data_out_CE);
data_out_CE <= (address(7) AND address(6) AND address(5) AND
NOT address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);
edge_romcs <= NOT (((NOT z80_rd AND NOT fastpage(1))
OR (NOT fastpage(1) AND NOT fastpage(2) AND NOT flashwrite)));
FTCPE_fastpage0: FTCPE port map (fastpage(0),fastpage_T(0),clock,fastpage_CLR(0),fastpage_PRE(0));
fastpage_T(0) <= ((NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_iorq AND fastpage(0) AND NOT z80_databus(5).PIN AND
bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr)
OR (NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_iorq AND NOT fastpage(0) AND z80_databus(5).PIN AND
bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr));
fastpage_CLR(0) <= (NOT reset AND ramrom);
fastpage_PRE(0) <= (NOT reset AND NOT ramrom);
FTCPE_fastpage1: FTCPE port map (fastpage(1),fastpage_T(1),clock,fastpage_CLR(1),fastpage_PRE(1));
fastpage_T(1) <= ((NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_iorq AND fastpage(1) AND bus_cnt(0) AND
NOT bus_cnt(1) AND NOT z80_wr AND NOT z80_databus(6).PIN)
OR (NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_iorq AND NOT fastpage(1) AND bus_cnt(0) AND
NOT bus_cnt(1) AND NOT z80_wr AND z80_databus(6).PIN));
fastpage_CLR(1) <= (NOT reset AND NOT residos);
fastpage_PRE(1) <= (NOT reset AND residos);
FDCPE_fastpage2: FDCPE port map (fastpage(2),z80_databus(7).PIN,clock,NOT reset,'0',fastpage_CE(2));
fastpage_CE(2) <= (NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);
FDCPE_flashwrite: FDCPE port map (flashwrite,flashwrite_D,clock,NOT reset,'0',flashwrite_CE);
flashwrite_D <= (NOT z80_databus(4).PIN AND z80_databus(7).PIN AND
z80_databus(5).PIN AND NOT z80_databus(6).PIN);
flashwrite_CE <= (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);
FTCPE_memory_bank0: FTCPE port map (memory_bank(0),memory_bank_T(0),clock,NOT reset,'0',memory_bank_CE(0));
memory_bank_T(0) <= (($OpTx$$OpTx$FX_DC$42_INV$432.EXP)
OR (NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND memory_bank(0) AND NOT z80_databus(0).PIN)
OR (NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT memory_bank(0) AND z80_databus(0).PIN)
OR (address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND NOT address(1) AND address(0) AND
address(4) AND NOT z80_databus(4).PIN AND memory_bank(0) AND
fastpage(0) AND hi_address(0) AND NOT hi_address(1)));
memory_bank_CE(0) <= (NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);
FDCPE_memory_bank1: FDCPE port map (memory_bank(1),z80_databus(1).PIN,clock,NOT reset,'0',memory_bank_CE(1));
memory_bank_CE(1) <= (NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);
FDCPE_memory_bank2: FDCPE port map (memory_bank(2),z80_databus(2).PIN,clock,NOT reset,'0',memory_bank_CE(2));
memory_bank_CE(2) <= (NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);
FDCPE_memory_bank3: FDCPE port map (memory_bank_I(3),z80_databus(3).PIN,clock,NOT reset,'0',memory_bank_CE(3));
memory_bank_CE(3) <= (NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);
memory_bank(3) <= memory_bank_I(3) when memory_bank_OE(3) = '1' else 'Z';
memory_bank_OE(3) <= NOT z80_mreq;
FDCPE_memory_bank4: FDCPE port map (memory_bank_I(4),z80_databus(4).PIN,clock,NOT reset,'0',memory_bank_CE(4));
memory_bank_CE(4) <= (NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);
memory_bank(4) <= memory_bank_I(4) when memory_bank_OE(4) = '1' else 'Z';
memory_bank_OE(4) <= NOT z80_mreq;
net_out <= NOT ((NOT comms_data AND NOT data_out));
FTCPE_nmi_enable: FTCPE port map (nmi_enable,nmi_enable_T,clock,NOT reset,'0');
nmi_enable_T <= ((rom_cs_OBUF.EXP)
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_databus(3).PIN AND z80_databus(4).PIN AND
NOT z80_iorq AND nmi_enable AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr)
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_databus(3).PIN AND NOT z80_iorq AND
NOT z80_databus(7).PIN AND nmi_enable AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr)
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_databus(3).PIN AND NOT z80_iorq AND nmi_enable AND
NOT z80_databus(5).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr)
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_databus(3).PIN AND NOT z80_iorq AND nmi_enable AND
bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND z80_databus(6).PIN));
ram_cs <= NOT (((reset AND NOT z80_mreq AND fastpage(2) AND NOT hi_address(0) AND
NOT z80_wr AND NOT hi_address(1))
OR (reset AND NOT z80_mreq AND NOT z80_rd AND NOT fastpage(0) AND
fastpage(1) AND NOT hi_address(0) AND NOT hi_address(1))));
rom_cs <= NOT (((z80_databus_6_IOBUFE.EXP)
OR (reset AND NOT z80_mreq AND flashwrite AND NOT hi_address(0) AND
NOT z80_wr AND NOT hi_address(1))));
rs_232out <= NOT ((comms_data AND data_out));
FDCPE_rx_register0: FDCPE port map (rx_register(0),spi_datain,clock,'0','0',rx_register_CE(0));
rx_register_CE(0) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));
FDCPE_rx_register1: FDCPE port map (rx_register(1),shift(0),clock,'0','0',rx_register_CE(1));
rx_register_CE(1) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));
FDCPE_rx_register2: FDCPE port map (rx_register(2),shift(1),clock,'0','0',rx_register_CE(2));
rx_register_CE(2) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));
FDCPE_rx_register3: FDCPE port map (rx_register(3),shift(2),clock,'0','0',rx_register_CE(3));
rx_register_CE(3) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));
FDCPE_rx_register4: FDCPE port map (rx_register(4),shift(3),clock,'0','0',rx_register_CE(4));
rx_register_CE(4) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));
FDCPE_rx_register5: FDCPE port map (rx_register(5),shift(4),clock,'0','0',rx_register_CE(5));
rx_register_CE(5) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));
FDCPE_rx_register6: FDCPE port map (rx_register(6),shift(5),clock,'0','0',rx_register_CE(6));
rx_register_CE(6) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));
FDCPE_rx_register7: FDCPE port map (rx_register(7),shift(6),clock,'0','0',rx_register_CE(7));
rx_register_CE(7) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));
FTCPE_shift0: FTCPE port map (shift(0),shift_T(0),clock,'0','0');
shift_T(0) <= ((NOT reset)
OR (NOT spi_tx(0))
OR (spi_datain AND shift(0))
OR (NOT spi_datain AND NOT shift(0))
OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));
FTCPE_shift1: FTCPE port map (shift(1),shift_T(1),clock,'0','0');
shift_T(1) <= ((NOT reset)
OR (NOT spi_tx(0))
OR (shift(0) AND shift(1))
OR (NOT shift(0) AND NOT shift(1))
OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));
FTCPE_shift2: FTCPE port map (shift(2),shift_T(2),clock,'0','0');
shift_T(2) <= ((NOT reset)
OR (NOT spi_tx(0))
OR (shift(1) AND shift(2))
OR (NOT shift(1) AND NOT shift(2))
OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));
FTCPE_shift3: FTCPE port map (shift(3),shift_T(3),clock,'0','0');
shift_T(3) <= ((NOT reset)
OR (NOT spi_tx(0))
OR (shift(2) AND shift(3))
OR (NOT shift(2) AND NOT shift(3))
OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));
FTCPE_shift4: FTCPE port map (shift(4),shift_T(4),clock,'0','0');
shift_T(4) <= ((NOT reset)
OR (NOT spi_tx(0))
OR (shift(3) AND shift(4))
OR (NOT shift(3) AND NOT shift(4))
OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));
FTCPE_shift5: FTCPE port map (shift(5),shift_T(5),clock,'0','0');
shift_T(5) <= ((NOT reset)
OR (NOT spi_tx(0))
OR (shift(4) AND shift(5))
OR (NOT shift(4) AND NOT shift(5))
OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));
FTCPE_shift6: FTCPE port map (shift(6),shift_T(6),clock,'0','0');
shift_T(6) <= ((NOT reset)
OR (NOT spi_tx(0))
OR (shift(5) AND shift(6))
OR (NOT shift(5) AND NOT shift(6))
OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));
FDCPE_spi_clock: FDCPE port map (spi_clock,spi_tx(0),clock,'0','0',reset);
FDCPE_spi_dataout: FDCPE port map (spi_dataout,spi_dataout_D,clock,'0','0');
spi_dataout_D <= ((z80_databus(7).PIN AND $OpTx$FX_SC$45)
OR (spi_dataout AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
OR (reset AND NOT spi_tx(0) AND tx_register(7) AND
NOT $OpTx$$OpTx$FX_DC$40_INV$431)
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_rd AND NOT z80_iorq AND NOT spi_tx(0) AND
$OpTx$$OpTx$FX_DC$40_INV$431));
FTCPE_spi_tx0: FTCPE port map (spi_tx(0),spi_tx_T(0),clock,'0','0');
spi_tx_T(0) <= ((spi_tx(1).EXP)
OR (reset AND spi_tx(0))
OR (reset AND spi_tx(1))
OR (reset AND spi_tx(2))
OR (reset AND spi_tx(3))
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_rd AND NOT z80_iorq));
FTCPE_spi_tx1: FTCPE port map (spi_tx(1),spi_tx_T(1),clock,'0','0');
spi_tx_T(1) <= ((msb_latch(1).EXP)
OR (reset AND NOT spi_tx(0) AND spi_tx(2))
OR (reset AND NOT spi_tx(0) AND spi_tx(3))
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_rd AND NOT z80_iorq AND NOT spi_tx(0))
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_iorq AND NOT spi_tx(0) AND bus_cnt(0) AND
NOT bus_cnt(1) AND NOT z80_wr));
FTCPE_spi_tx2: FTCPE port map (spi_tx(2),spi_tx_T(2),clock,'0','0');
spi_tx_T(2) <= ((reset AND NOT spi_tx(0) AND NOT spi_tx(1) AND spi_tx(2))
OR (reset AND NOT spi_tx(0) AND NOT spi_tx(1) AND spi_tx(3))
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_rd AND NOT z80_iorq AND NOT spi_tx(0) AND
NOT spi_tx(1))
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_iorq AND NOT spi_tx(0) AND NOT spi_tx(1) AND
bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr));
FTCPE_spi_tx3: FTCPE port map (spi_tx(3),spi_tx_T(3),clock,'0','0');
spi_tx_T(3) <= ((reset AND NOT spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
spi_tx(3))
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_rd AND NOT z80_iorq AND NOT spi_tx(0) AND
NOT spi_tx(1) AND NOT spi_tx(2))
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_iorq AND NOT spi_tx(0) AND NOT spi_tx(1) AND
NOT spi_tx(2) AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr));
FTCPE_tx_register0: FTCPE port map (tx_register(0),tx_register_T(0),clock,'0','0');
tx_register_T(0) <= ((reset AND NOT spi_tx(0) AND spi_tx(1) AND NOT tx_register(0))
OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND NOT tx_register(0))
OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND NOT tx_register(0))
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND reset AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND
NOT z80_wr AND NOT tx_register(0)));
FDCPE_tx_register1: FDCPE port map (tx_register(1),tx_register_D(1),clock,'0','0');
tx_register_D(1) <= ((z80_databus(0).PIN AND $OpTx$FX_SC$45)
OR (tx_register(1) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(0))
OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(0))
OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(0)));
FDCPE_tx_register2: FDCPE port map (tx_register(2),tx_register_D(2),clock,'0','0');
tx_register_D(2) <= ((z80_databus(1).PIN AND $OpTx$FX_SC$45)
OR (tx_register(2) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(1))
OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(1))
OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(1)));
FDCPE_tx_register3: FDCPE port map (tx_register(3),tx_register_D(3),clock,'0','0');
tx_register_D(3) <= ((z80_databus(2).PIN AND $OpTx$FX_SC$45)
OR (tx_register(3) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(2))
OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(2))
OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(2)));
FDCPE_tx_register4: FDCPE port map (tx_register(4),tx_register_D(4),clock,'0','0');
tx_register_D(4) <= ((z80_databus(3).PIN AND $OpTx$FX_SC$45)
OR (tx_register(4) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(3))
OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(3))
OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(3)));
FDCPE_tx_register5: FDCPE port map (tx_register(5),tx_register_D(5),clock,'0','0');
tx_register_D(5) <= ((z80_databus(4).PIN AND $OpTx$FX_SC$45)
OR (tx_register(5) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(4))
OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(4))
OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(4)));
FDCPE_tx_register6: FDCPE port map (tx_register(6),tx_register_D(6),clock,'0','0');
tx_register_D(6) <= ((z80_databus(5).PIN AND $OpTx$FX_SC$45)
OR (tx_register(6) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(5))
OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(5))
OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(5)));
FDCPE_tx_register7: FDCPE port map (tx_register(7),tx_register_D(7),clock,'0','0');
tx_register_D(7) <= ((tx_register(7) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
OR (z80_databus(6).PIN AND $OpTx$FX_SC$45)
OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(6))
OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(6))
OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(6)));
FDCPE_wait_cnt0: FDCPE port map (wait_cnt(0),wait_cnt_D(0),clock,NOT reset,'0');
wait_cnt_D(0) <= ((wait_cnt(0) AND net_in)
OR (NOT wait_cnt(0) AND wait_cnt(1) AND NOT net_in)
OR (address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
NOT address(4) AND NOT z80_iorq AND net_in AND NOT z80_databus(5).PIN AND
NOT if1_enable AND NOT z80_wr));
FTCPE_wait_cnt1: FTCPE port map (wait_cnt(1),wait_cnt_T(1),clock,NOT reset,'0');
wait_cnt_T(1) <= ((NOT wait_cnt(0) AND wait_cnt(1) AND NOT net_in)
OR (address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
NOT address(4) AND NOT z80_iorq AND NOT wait_cnt(1) AND net_in AND
NOT z80_databus(5).PIN AND NOT if1_enable AND NOT z80_wr));
z80_databus_I(0) <= NOT (((z80_databus_2_IOBUFE.EXP)
OR (EXP7_.EXP)
OR (NOT address(3) AND NOT net_in)
OR (NOT address(2) AND NOT net_in)
OR (NOT address(1) AND NOT net_in)
OR (NOT address(0) AND NOT net_in)));
z80_databus(0) <= z80_databus_I(0) when z80_databus_OE(0) = '1' else 'Z';
z80_databus_OE(0) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
NOT z80_iorq AND $OpTx$FX_DC$41);
z80_databus_I(1) <= ((wait_cnt(0).EXP)
OR (NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND memory_bank(1) AND NOT z80_rd AND NOT z80_iorq)
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_rd AND NOT z80_iorq AND rx_register(1)));
z80_databus(1) <= z80_databus_I(1) when z80_databus_OE(1) = '1' else 'Z';
z80_databus_OE(1) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
NOT z80_iorq AND $OpTx$FX_DC$41);
z80_databus_I(2) <= ((NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND memory_bank(2) AND NOT z80_rd AND NOT z80_iorq)
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_rd AND NOT z80_iorq AND rx_register(2))
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_rd AND NOT z80_iorq AND NOT kempston_enable AND
NOT kempston(2)));
z80_databus(2) <= z80_databus_I(2) when z80_databus_OE(2) = '1' else 'Z';
z80_databus_OE(2) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
NOT z80_iorq AND $OpTx$FX_DC$41);
z80_databus_I(3) <= NOT (((EXP6_.EXP)
OR (z80_databus_1_IOBUFE.EXP)
OR (NOT address(3) AND dtr_in)
OR (NOT address(2) AND dtr_in)
OR (NOT address(1) AND dtr_in)
OR (NOT address(0) AND dtr_in)));
z80_databus(3) <= z80_databus_I(3) when z80_databus_OE(3) = '1' else 'Z';
z80_databus_OE(3) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
NOT z80_iorq AND $OpTx$FX_DC$41);
z80_databus_I(4) <= ((NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND memory_bank(4) AND NOT z80_rd AND NOT z80_iorq)
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_rd AND NOT z80_iorq AND rx_register(4))
OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_rd AND NOT z80_iorq AND NOT kempston_enable AND
memory_bank(3).PIN));
z80_databus(4) <= z80_databus_I(4) when z80_databus_OE(4) = '1' else 'Z';
z80_databus_OE(4) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
NOT z80_iorq AND $OpTx$FX_DC$41);
z80_databus_I(5) <= ((NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_rd AND NOT z80_iorq AND fastpage(0))
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_rd AND NOT z80_iorq AND rx_register(5)));
z80_databus(5) <= z80_databus_I(5) when z80_databus_OE(5) = '1' else 'Z';
z80_databus_OE(5) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
NOT z80_iorq AND $OpTx$FX_DC$41);
z80_databus_I(6) <= ((NOT address(7) AND address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_rd AND NOT z80_iorq AND fastpage(1))
OR (NOT address(7) AND NOT address(6) AND address(5) AND
address(3) AND address(2) AND address(1) AND address(0) AND
address(4) AND NOT z80_rd AND NOT z80_iorq AND rx_register(6)));
z80_databus(6) <= z80_databus_I(6) when z80_databus_OE(6) = '1' else 'Z';
z80_databus_OE(6) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
NOT z80_iorq AND $OpTx$FX_DC$41);
z80_databus_I(7) <= NOT (((EXP8_.EXP)
OR (msb_latch(0).EXP)
OR (address(7) AND rs_232in)
OR (NOT address(5) AND rs_232in)
OR (NOT address(1) AND rs_232in)
OR (NOT address(4) AND rs_232in)));
z80_databus(7) <= z80_databus_I(7) when z80_databus_OE(7) = '1' else 'Z';
z80_databus_OE(7) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
NOT z80_iorq AND $OpTx$FX_DC$41);
z80_nmi_I <= '0';
z80_nmi <= z80_nmi_I when z80_nmi_OE = '1' else 'Z';
z80_nmi_OE <= (nmi_enable AND NOT rs_232in);
z80_wait_I <= '0';
z80_wait <= z80_wait_I when z80_wait_OE = '1' else 'Z';
z80_wait_OE <= NOT ((NOT wait_cnt(0) AND NOT wait_cnt(1)));
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XC9572XL-5-VQ64
-----------------------------------------------
/48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 \
| 49 32 |
| 50 31 |
| 51 30 |
| 52 29 |
| 53 28 |
| 54 27 |
| 55 26 |
| 56 XC9572XL-5-VQ64 25 |
| 57 24 |
| 58 23 |
| 59 22 |
| 60 21 |
| 61 20 |
| 62 19 |
| 63 18 |
| 64 17 |
\ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 /
-----------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 spi_datain 33 hi_address<1>
2 spi_clock 34 hi_address<0>
3 VCC 35 kempston<0>
4 OUT1_reg<1> 36 kempston<1>
5 spi_dataout 37 VCC
6 OUT1_reg<0> 38 z80_wait
7 memory_bank<2> 39 kempston<2>
8 memory_bank<1> 40 ramrom
9 address<4> 41 GND
10 z80_wr 42 net_in
11 z80_rd 43 z80_nmi
12 address<3> 44 rs_232in
13 z80_databus<4> 45 cts_out
14 GND 46 dtr_in
15 z80_databus<3> 47 residos
16 clock 48 net_out
17 z80_databus<2> 49 memory_bank<0>
18 z80_databus<1> 50 z80_databus<5>
19 z80_databus<0> 51 kempston_enable
20 ram_cs 52 if1_enable
21 GND 53 TDO
22 address<7> 54 GND
23 address<5> 55 VCC
24 z80_iorq 56 rs_232out
25 address<6> 57 address<2>
26 VCC 58 memory_bank<3>
27 edge_romcs 59 z80_databus<6>
28 TDI 60 z80_databus<7>
29 TMS 61 rom_cs
30 TCK 62 address<1>
31 z80_mreq 63 address<0>
32 reset 64 memory_bank<4>
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
KPR = Unused I/O with weak keeper (leave unconnected)
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572xl-5-VQ64
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : FAST
Power Mode : STD
Ground on Unused IOs : OFF
Set I/O Pin Termination : KEEPER
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
Input Limit : 19
Pterm Limit : 25