Equations

********** Mapped Logic **********

$OpTx$$OpTx$FX_DC$40_INV$431 <= (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3));

$OpTx$$OpTx$FX_DC$42_INV$432 <= ((reset AND NOT spi_tx(0) AND spi_tx(1))
      OR (reset AND NOT spi_tx(0) AND spi_tx(2))
      OR (reset AND NOT spi_tx(0) AND spi_tx(3))
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND
      NOT z80_wr));

$OpTx$FX_DC$41 <= ((NOT address(7) AND address(5) AND address(3) AND
      address(4))
      OR (NOT address(7) AND NOT address(6) AND address(3) AND
      address(4) AND NOT kempston_enable)
      OR (address(7) AND address(6) AND address(5) AND
      address(3) AND NOT address(4) AND NOT if1_enable)
      OR (address(7) AND address(6) AND address(5) AND
      NOT address(3) AND address(4) AND NOT if1_enable));

$OpTx$FX_SC$45 <= ((NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_iorq AND spi_tx(0) AND bus_cnt(0) AND
      NOT bus_cnt(1) AND NOT z80_wr)
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_iorq AND NOT spi_tx(1) AND NOT spi_tx(2) AND
      NOT spi_tx(3) AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr));

FTCPE_OUT1_reg0: FTCPE port map (OUT1_reg(0),OUT1_reg_T(0),clock,'0','0');
     OUT1_reg_T(0) <= ((spi_dataout_OBUF.EXP)
      OR (spi_tx(3).EXP)
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND z80_databus(4).PIN AND NOT z80_iorq AND
      NOT z80_databus(0).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(0))
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_iorq AND NOT z80_databus(7).PIN AND
      NOT z80_databus(0).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(0))
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_iorq AND z80_databus(0).PIN AND
      NOT z80_databus(5).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND NOT OUT1_reg(0))
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_iorq AND NOT z80_databus(0).PIN AND
      NOT z80_databus(5).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(0))
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_iorq AND NOT z80_databus(0).PIN AND
      bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(0) AND
      z80_databus(6).PIN));

FTCPE_OUT1_reg1: FTCPE port map (OUT1_reg(1),OUT1_reg_T(1),clock,'0','0');
     OUT1_reg_T(1) <= ((spi_clock_OBUF.EXP)
      OR (flashwrite.EXP)
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND z80_databus(4).PIN AND NOT z80_databus(1).PIN AND
      NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(1))
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND z80_databus(1).PIN AND NOT z80_iorq AND
      NOT z80_databus(5).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND NOT OUT1_reg(1))
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_databus(1).PIN AND NOT z80_iorq AND
      NOT z80_databus(7).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(1))
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_databus(1).PIN AND NOT z80_iorq AND
      NOT z80_databus(5).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(1))
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_databus(1).PIN AND NOT z80_iorq AND
      bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND OUT1_reg(1) AND
      z80_databus(6).PIN));

FDCPE_bus_cnt0: FDCPE port map (bus_cnt(0),bus_cnt_D(0),clock,'0','0',reset);
bus_cnt_D(0) <= (NOT z80_iorq AND NOT bus_cnt(0) AND NOT z80_wr);

FDCPE_bus_cnt1: FDCPE port map (bus_cnt(1),bus_cnt_D(1),clock,'0','0',reset);
bus_cnt_D(1) <= ((NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr)
OR (NOT z80_iorq AND NOT bus_cnt(0) AND bus_cnt(1) AND NOT z80_wr));

FDCPE_comms_data: FDCPE port map (comms_data,z80_databus(0).PIN,clock,NOT reset,'0',comms_data_CE);
     comms_data_CE <= (address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      NOT address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);

FDCPE_cts_out: FDCPE port map (cts_out,NOT z80_databus(4).PIN,clock,'0',NOT reset,cts_out_CE);
     cts_out_CE <= (address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      NOT address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);

FDCPE_data_out: FDCPE port map (data_out,z80_databus(0).PIN,clock,'0',NOT reset,data_out_CE);
     data_out_CE <= (address(7) AND address(6) AND address(5) AND
      NOT address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);

edge_romcs <= NOT (((NOT z80_rd AND NOT fastpage(1))
OR (NOT fastpage(1) AND NOT fastpage(2) AND NOT flashwrite)));

FTCPE_fastpage0: FTCPE port map (fastpage(0),fastpage_T(0),clock,fastpage_CLR(0),fastpage_PRE(0));
     fastpage_T(0) <= ((NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_iorq AND fastpage(0) AND NOT z80_databus(5).PIN AND
      bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr)
      OR (NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_iorq AND NOT fastpage(0) AND z80_databus(5).PIN AND
      bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr));
     fastpage_CLR(0) <= (NOT reset AND ramrom);
     fastpage_PRE(0) <= (NOT reset AND NOT ramrom);

FTCPE_fastpage1: FTCPE port map (fastpage(1),fastpage_T(1),clock,fastpage_CLR(1),fastpage_PRE(1));
     fastpage_T(1) <= ((NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_iorq AND fastpage(1) AND bus_cnt(0) AND
      NOT bus_cnt(1) AND NOT z80_wr AND NOT z80_databus(6).PIN)
      OR (NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_iorq AND NOT fastpage(1) AND bus_cnt(0) AND
      NOT bus_cnt(1) AND NOT z80_wr AND z80_databus(6).PIN));
     fastpage_CLR(1) <= (NOT reset AND NOT residos);
     fastpage_PRE(1) <= (NOT reset AND residos);

FDCPE_fastpage2: FDCPE port map (fastpage(2),z80_databus(7).PIN,clock,NOT reset,'0',fastpage_CE(2));
     fastpage_CE(2) <= (NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);

FDCPE_flashwrite: FDCPE port map (flashwrite,flashwrite_D,clock,NOT reset,'0',flashwrite_CE);
     flashwrite_D <= (NOT z80_databus(4).PIN AND z80_databus(7).PIN AND
      z80_databus(5).PIN AND NOT z80_databus(6).PIN);
     flashwrite_CE <= (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);

FTCPE_memory_bank0: FTCPE port map (memory_bank(0),memory_bank_T(0),clock,NOT reset,'0',memory_bank_CE(0));
     memory_bank_T(0) <= (($OpTx$$OpTx$FX_DC$42_INV$432.EXP)
      OR (NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND memory_bank(0) AND NOT z80_databus(0).PIN)
      OR (NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT memory_bank(0) AND z80_databus(0).PIN)
      OR (address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND NOT address(1) AND address(0) AND
      address(4) AND NOT z80_databus(4).PIN AND memory_bank(0) AND
      fastpage(0) AND hi_address(0) AND NOT hi_address(1)));
     memory_bank_CE(0) <= (NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);

FDCPE_memory_bank1: FDCPE port map (memory_bank(1),z80_databus(1).PIN,clock,NOT reset,'0',memory_bank_CE(1));
     memory_bank_CE(1) <= (NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);

FDCPE_memory_bank2: FDCPE port map (memory_bank(2),z80_databus(2).PIN,clock,NOT reset,'0',memory_bank_CE(2));
     memory_bank_CE(2) <= (NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);

FDCPE_memory_bank3: FDCPE port map (memory_bank_I(3),z80_databus(3).PIN,clock,NOT reset,'0',memory_bank_CE(3));
     memory_bank_CE(3) <= (NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);
     memory_bank(3) <= memory_bank_I(3) when memory_bank_OE(3) = '1' else 'Z';
     memory_bank_OE(3) <= NOT z80_mreq;

FDCPE_memory_bank4: FDCPE port map (memory_bank_I(4),z80_databus(4).PIN,clock,NOT reset,'0',memory_bank_CE(4));
     memory_bank_CE(4) <= (NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr);
     memory_bank(4) <= memory_bank_I(4) when memory_bank_OE(4) = '1' else 'Z';
     memory_bank_OE(4) <= NOT z80_mreq;

net_out <= NOT ((NOT comms_data AND NOT data_out));

FTCPE_nmi_enable: FTCPE port map (nmi_enable,nmi_enable_T,clock,NOT reset,'0');
     nmi_enable_T <= ((rom_cs_OBUF.EXP)
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_databus(3).PIN AND z80_databus(4).PIN AND
      NOT z80_iorq AND nmi_enable AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr)
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_databus(3).PIN AND NOT z80_iorq AND
      NOT z80_databus(7).PIN AND nmi_enable AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr)
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_databus(3).PIN AND NOT z80_iorq AND nmi_enable AND
      NOT z80_databus(5).PIN AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr)
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_databus(3).PIN AND NOT z80_iorq AND nmi_enable AND
      bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr AND z80_databus(6).PIN));

ram_cs <= NOT (((reset AND NOT z80_mreq AND fastpage(2) AND NOT hi_address(0) AND
      NOT z80_wr AND NOT hi_address(1))
      OR (reset AND NOT z80_mreq AND NOT z80_rd AND NOT fastpage(0) AND
      fastpage(1) AND NOT hi_address(0) AND NOT hi_address(1))));

rom_cs <= NOT (((z80_databus_6_IOBUFE.EXP)
OR (reset AND NOT z80_mreq AND flashwrite AND NOT hi_address(0) AND
NOT z80_wr AND NOT hi_address(1))));

rs_232out <= NOT ((comms_data AND data_out));

FDCPE_rx_register0: FDCPE port map (rx_register(0),spi_datain,clock,'0','0',rx_register_CE(0));
rx_register_CE(0) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));

FDCPE_rx_register1: FDCPE port map (rx_register(1),shift(0),clock,'0','0',rx_register_CE(1));
rx_register_CE(1) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));

FDCPE_rx_register2: FDCPE port map (rx_register(2),shift(1),clock,'0','0',rx_register_CE(2));
rx_register_CE(2) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));

FDCPE_rx_register3: FDCPE port map (rx_register(3),shift(2),clock,'0','0',rx_register_CE(3));
rx_register_CE(3) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));

FDCPE_rx_register4: FDCPE port map (rx_register(4),shift(3),clock,'0','0',rx_register_CE(4));
rx_register_CE(4) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));

FDCPE_rx_register5: FDCPE port map (rx_register(5),shift(4),clock,'0','0',rx_register_CE(5));
rx_register_CE(5) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));

FDCPE_rx_register6: FDCPE port map (rx_register(6),shift(5),clock,'0','0',rx_register_CE(6));
rx_register_CE(6) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));

FDCPE_rx_register7: FDCPE port map (rx_register(7),shift(6),clock,'0','0',rx_register_CE(7));
rx_register_CE(7) <= (reset AND spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
NOT spi_tx(3));

FTCPE_shift0: FTCPE port map (shift(0),shift_T(0),clock,'0','0');
     shift_T(0) <= ((NOT reset)
      OR (NOT spi_tx(0))
      OR (spi_datain AND shift(0))
      OR (NOT spi_datain AND NOT shift(0))
      OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));

FTCPE_shift1: FTCPE port map (shift(1),shift_T(1),clock,'0','0');
     shift_T(1) <= ((NOT reset)
      OR (NOT spi_tx(0))
      OR (shift(0) AND shift(1))
      OR (NOT shift(0) AND NOT shift(1))
      OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));

FTCPE_shift2: FTCPE port map (shift(2),shift_T(2),clock,'0','0');
     shift_T(2) <= ((NOT reset)
      OR (NOT spi_tx(0))
      OR (shift(1) AND shift(2))
      OR (NOT shift(1) AND NOT shift(2))
      OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));

FTCPE_shift3: FTCPE port map (shift(3),shift_T(3),clock,'0','0');
     shift_T(3) <= ((NOT reset)
      OR (NOT spi_tx(0))
      OR (shift(2) AND shift(3))
      OR (NOT shift(2) AND NOT shift(3))
      OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));

FTCPE_shift4: FTCPE port map (shift(4),shift_T(4),clock,'0','0');
     shift_T(4) <= ((NOT reset)
      OR (NOT spi_tx(0))
      OR (shift(3) AND shift(4))
      OR (NOT shift(3) AND NOT shift(4))
      OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));

FTCPE_shift5: FTCPE port map (shift(5),shift_T(5),clock,'0','0');
     shift_T(5) <= ((NOT reset)
      OR (NOT spi_tx(0))
      OR (shift(4) AND shift(5))
      OR (NOT shift(4) AND NOT shift(5))
      OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));

FTCPE_shift6: FTCPE port map (shift(6),shift_T(6),clock,'0','0');
     shift_T(6) <= ((NOT reset)
      OR (NOT spi_tx(0))
      OR (shift(5) AND shift(6))
      OR (NOT shift(5) AND NOT shift(6))
      OR (NOT spi_tx(1) AND NOT spi_tx(2) AND NOT spi_tx(3)));

FDCPE_spi_clock: FDCPE port map (spi_clock,spi_tx(0),clock,'0','0',reset);

FDCPE_spi_dataout: FDCPE port map (spi_dataout,spi_dataout_D,clock,'0','0');
     spi_dataout_D <= ((z80_databus(7).PIN AND $OpTx$FX_SC$45)
      OR (spi_dataout AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
      OR (reset AND NOT spi_tx(0) AND tx_register(7) AND
      NOT $OpTx$$OpTx$FX_DC$40_INV$431)
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_rd AND NOT z80_iorq AND NOT spi_tx(0) AND
      $OpTx$$OpTx$FX_DC$40_INV$431));

FTCPE_spi_tx0: FTCPE port map (spi_tx(0),spi_tx_T(0),clock,'0','0');
     spi_tx_T(0) <= ((spi_tx(1).EXP)
      OR (reset AND spi_tx(0))
      OR (reset AND spi_tx(1))
      OR (reset AND spi_tx(2))
      OR (reset AND spi_tx(3))
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_rd AND NOT z80_iorq));

FTCPE_spi_tx1: FTCPE port map (spi_tx(1),spi_tx_T(1),clock,'0','0');
     spi_tx_T(1) <= ((msb_latch(1).EXP)
      OR (reset AND NOT spi_tx(0) AND spi_tx(2))
      OR (reset AND NOT spi_tx(0) AND spi_tx(3))
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_rd AND NOT z80_iorq AND NOT spi_tx(0))
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_iorq AND NOT spi_tx(0) AND bus_cnt(0) AND
      NOT bus_cnt(1) AND NOT z80_wr));

FTCPE_spi_tx2: FTCPE port map (spi_tx(2),spi_tx_T(2),clock,'0','0');
     spi_tx_T(2) <= ((reset AND NOT spi_tx(0) AND NOT spi_tx(1) AND spi_tx(2))
      OR (reset AND NOT spi_tx(0) AND NOT spi_tx(1) AND spi_tx(3))
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_rd AND NOT z80_iorq AND NOT spi_tx(0) AND
      NOT spi_tx(1))
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_iorq AND NOT spi_tx(0) AND NOT spi_tx(1) AND
      bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr));

FTCPE_spi_tx3: FTCPE port map (spi_tx(3),spi_tx_T(3),clock,'0','0');
     spi_tx_T(3) <= ((reset AND NOT spi_tx(0) AND NOT spi_tx(1) AND NOT spi_tx(2) AND
      spi_tx(3))
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_rd AND NOT z80_iorq AND NOT spi_tx(0) AND
      NOT spi_tx(1) AND NOT spi_tx(2))
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_iorq AND NOT spi_tx(0) AND NOT spi_tx(1) AND
      NOT spi_tx(2) AND bus_cnt(0) AND NOT bus_cnt(1) AND NOT z80_wr));

FTCPE_tx_register0: FTCPE port map (tx_register(0),tx_register_T(0),clock,'0','0');
     tx_register_T(0) <= ((reset AND NOT spi_tx(0) AND spi_tx(1) AND NOT tx_register(0))
      OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND NOT tx_register(0))
      OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND NOT tx_register(0))
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND reset AND NOT z80_iorq AND bus_cnt(0) AND NOT bus_cnt(1) AND
      NOT z80_wr AND NOT tx_register(0)));

FDCPE_tx_register1: FDCPE port map (tx_register(1),tx_register_D(1),clock,'0','0');
     tx_register_D(1) <= ((z80_databus(0).PIN AND $OpTx$FX_SC$45)
      OR (tx_register(1) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
      OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(0))
      OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(0))
      OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(0)));

FDCPE_tx_register2: FDCPE port map (tx_register(2),tx_register_D(2),clock,'0','0');
     tx_register_D(2) <= ((z80_databus(1).PIN AND $OpTx$FX_SC$45)
      OR (tx_register(2) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
      OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(1))
      OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(1))
      OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(1)));

FDCPE_tx_register3: FDCPE port map (tx_register(3),tx_register_D(3),clock,'0','0');
     tx_register_D(3) <= ((z80_databus(2).PIN AND $OpTx$FX_SC$45)
      OR (tx_register(3) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
      OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(2))
      OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(2))
      OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(2)));

FDCPE_tx_register4: FDCPE port map (tx_register(4),tx_register_D(4),clock,'0','0');
     tx_register_D(4) <= ((z80_databus(3).PIN AND $OpTx$FX_SC$45)
      OR (tx_register(4) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
      OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(3))
      OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(3))
      OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(3)));

FDCPE_tx_register5: FDCPE port map (tx_register(5),tx_register_D(5),clock,'0','0');
     tx_register_D(5) <= ((z80_databus(4).PIN AND $OpTx$FX_SC$45)
      OR (tx_register(5) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
      OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(4))
      OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(4))
      OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(4)));

FDCPE_tx_register6: FDCPE port map (tx_register(6),tx_register_D(6),clock,'0','0');
     tx_register_D(6) <= ((z80_databus(5).PIN AND $OpTx$FX_SC$45)
      OR (tx_register(6) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
      OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(5))
      OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(5))
      OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(5)));

FDCPE_tx_register7: FDCPE port map (tx_register(7),tx_register_D(7),clock,'0','0');
     tx_register_D(7) <= ((tx_register(7) AND NOT $OpTx$$OpTx$FX_DC$42_INV$432)
      OR (z80_databus(6).PIN AND $OpTx$FX_SC$45)
      OR (reset AND NOT spi_tx(0) AND spi_tx(1) AND tx_register(6))
      OR (reset AND NOT spi_tx(0) AND spi_tx(2) AND tx_register(6))
      OR (reset AND NOT spi_tx(0) AND spi_tx(3) AND tx_register(6)));

FDCPE_wait_cnt0: FDCPE port map (wait_cnt(0),wait_cnt_D(0),clock,NOT reset,'0');
     wait_cnt_D(0) <= ((wait_cnt(0) AND net_in)
      OR (NOT wait_cnt(0) AND wait_cnt(1) AND NOT net_in)
      OR (address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      NOT address(4) AND NOT z80_iorq AND net_in AND NOT z80_databus(5).PIN AND
      NOT if1_enable AND NOT z80_wr));

FTCPE_wait_cnt1: FTCPE port map (wait_cnt(1),wait_cnt_T(1),clock,NOT reset,'0');
     wait_cnt_T(1) <= ((NOT wait_cnt(0) AND wait_cnt(1) AND NOT net_in)
      OR (address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      NOT address(4) AND NOT z80_iorq AND NOT wait_cnt(1) AND net_in AND
      NOT z80_databus(5).PIN AND NOT if1_enable AND NOT z80_wr));

z80_databus_I(0) <= NOT (((z80_databus_2_IOBUFE.EXP)
      OR (EXP7_.EXP)
      OR (NOT address(3) AND NOT net_in)
      OR (NOT address(2) AND NOT net_in)
      OR (NOT address(1) AND NOT net_in)
      OR (NOT address(0) AND NOT net_in)));
     z80_databus(0) <= z80_databus_I(0) when z80_databus_OE(0) = '1' else 'Z';
     z80_databus_OE(0) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
      NOT z80_iorq AND $OpTx$FX_DC$41);

z80_databus_I(1) <= ((wait_cnt(0).EXP)
      OR (NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND memory_bank(1) AND NOT z80_rd AND NOT z80_iorq)
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_rd AND NOT z80_iorq AND rx_register(1)));
     z80_databus(1) <= z80_databus_I(1) when z80_databus_OE(1) = '1' else 'Z';
     z80_databus_OE(1) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
      NOT z80_iorq AND $OpTx$FX_DC$41);

z80_databus_I(2) <= ((NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND memory_bank(2) AND NOT z80_rd AND NOT z80_iorq)
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_rd AND NOT z80_iorq AND rx_register(2))
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_rd AND NOT z80_iorq AND NOT kempston_enable AND
      NOT kempston(2)));
     z80_databus(2) <= z80_databus_I(2) when z80_databus_OE(2) = '1' else 'Z';
     z80_databus_OE(2) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
      NOT z80_iorq AND $OpTx$FX_DC$41);

z80_databus_I(3) <= NOT (((EXP6_.EXP)
      OR (z80_databus_1_IOBUFE.EXP)
      OR (NOT address(3) AND dtr_in)
      OR (NOT address(2) AND dtr_in)
      OR (NOT address(1) AND dtr_in)
      OR (NOT address(0) AND dtr_in)));
     z80_databus(3) <= z80_databus_I(3) when z80_databus_OE(3) = '1' else 'Z';
     z80_databus_OE(3) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
      NOT z80_iorq AND $OpTx$FX_DC$41);

z80_databus_I(4) <= ((NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND memory_bank(4) AND NOT z80_rd AND NOT z80_iorq)
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_rd AND NOT z80_iorq AND rx_register(4))
      OR (NOT address(7) AND NOT address(6) AND NOT address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_rd AND NOT z80_iorq AND NOT kempston_enable AND
      memory_bank(3).PIN));
     z80_databus(4) <= z80_databus_I(4) when z80_databus_OE(4) = '1' else 'Z';
     z80_databus_OE(4) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
      NOT z80_iorq AND $OpTx$FX_DC$41);

z80_databus_I(5) <= ((NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_rd AND NOT z80_iorq AND fastpage(0))
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_rd AND NOT z80_iorq AND rx_register(5)));
     z80_databus(5) <= z80_databus_I(5) when z80_databus_OE(5) = '1' else 'Z';
     z80_databus_OE(5) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
      NOT z80_iorq AND $OpTx$FX_DC$41);

z80_databus_I(6) <= ((NOT address(7) AND address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_rd AND NOT z80_iorq AND fastpage(1))
      OR (NOT address(7) AND NOT address(6) AND address(5) AND
      address(3) AND address(2) AND address(1) AND address(0) AND
      address(4) AND NOT z80_rd AND NOT z80_iorq AND rx_register(6)));
     z80_databus(6) <= z80_databus_I(6) when z80_databus_OE(6) = '1' else 'Z';
     z80_databus_OE(6) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
      NOT z80_iorq AND $OpTx$FX_DC$41);

z80_databus_I(7) <= NOT (((EXP8_.EXP)
      OR (msb_latch(0).EXP)
      OR (address(7) AND rs_232in)
      OR (NOT address(5) AND rs_232in)
      OR (NOT address(1) AND rs_232in)
      OR (NOT address(4) AND rs_232in)));
     z80_databus(7) <= z80_databus_I(7) when z80_databus_OE(7) = '1' else 'Z';
     z80_databus_OE(7) <= (address(2) AND address(1) AND address(0) AND NOT z80_rd AND
      NOT z80_iorq AND $OpTx$FX_DC$41);

z80_nmi_I <= '0';
z80_nmi <= z80_nmi_I when z80_nmi_OE = '1' else 'Z';
z80_nmi_OE <= (nmi_enable AND NOT rs_232in);

z80_wait_I <= '0';
z80_wait <= z80_wait_I when z80_wait_OE = '1' else 'Z';
z80_wait_OE <= NOT ((NOT wait_cnt(0) AND NOT wait_cnt(1)));