Timing Report

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Design Name X9572_zxmmc2
Device, Speed (SpeedFile Version) XC9572XL, -5 (3.0)
Date Created Sun Jan 11 22:51:24 2009
Created By Timing Report Generator: version K.34
Copyright Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 9.000 ns.
Max. Clock Frequency (fSYSTEM) 111.111 MHz.
Limited by Cycle Time for clock
Clock to Setup (tCYC) 9.000 ns.
Pad to Pad Delay (tPD) 10.400 ns.
Setup to Clock at the Pad (tSU) 7.100 ns.
Clock Pad to Output Pad Delay (tCO) 8.900 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 9.0 220 220
AUTO_TS_P2P 0.0 10.4 145 145
AUTO_TS_P2F 0.0 8.2 392 392
AUTO_TS_F2P 0.0 7.8 42 42


Constraint: TS1000

Description: PERIOD:PERIOD_clock:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
bus_cnt<0>.Q to spi_dataout.D 0.000 9.000 -9.000
bus_cnt<0>.Q to tx_register<1>.D 0.000 9.000 -9.000
bus_cnt<0>.Q to tx_register<2>.D 0.000 9.000 -9.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
address<3> to z80_databus<0> 0.000 10.400 -10.400
address<3> to z80_databus<1> 0.000 10.400 -10.400
address<3> to z80_databus<2> 0.000 10.400 -10.400


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
address<0> to spi_dataout.D 0.000 8.200 -8.200
address<0> to tx_register<1>.D 0.000 8.200 -8.200
address<0> to tx_register<2>.D 0.000 8.200 -8.200


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
nmi_enable.Q to z80_nmi 0.000 7.800 -7.800
wait_cnt<0>.Q to z80_wait 0.000 7.800 -7.800
wait_cnt<1>.Q to z80_wait 0.000 7.800 -7.800



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
clock 111.111 Limited by Cycle Time for clock

Setup/Hold Times for Clocks

Setup/Hold Times for Clock clock
Source Pad Setup to clk (edge) Hold to clk (edge)
address<0> 7.100 0.000
address<1> 7.100 0.000
address<2> 7.100 0.000
address<3> 7.100 0.000
address<4> 7.100 0.000
address<5> 7.100 0.000
address<6> 7.100 0.000
address<7> 7.100 0.000
hi_address<0> 4.400 0.000
hi_address<1> 4.400 0.000
if1_enable 3.700 0.000
net_in 3.700 0.000
reset 7.100 0.000
spi_datain 3.700 0.000
z80_databus<0> 4.400 0.000
z80_databus<1> 4.400 0.000
z80_databus<2> 3.700 0.000
z80_databus<3> 4.400 0.000
z80_databus<4> 4.400 0.000
z80_databus<5> 4.400 0.000
z80_databus<6> 4.400 0.000
z80_databus<7> 4.400 0.000
z80_iorq 7.100 0.000
z80_rd 3.700 0.000
z80_wr 7.100 0.000


Clock to Pad Timing

Clock clock to Pad
Destination Pad Clock (edge) to Pad
z80_nmi 8.900
z80_wait 8.900
z80_databus<0> 7.900
z80_databus<3> 7.900
z80_databus<7> 7.900
rom_cs 7.600
edge_romcs 6.900
net_out 6.900
ram_cs 6.900
rs_232out 6.900
z80_databus<1> 6.900
z80_databus<2> 6.900
z80_databus<4> 6.900
z80_databus<5> 6.900
z80_databus<6> 6.900
OUT1_reg<0> 3.500
OUT1_reg<1> 3.500
cts_out 3.500
memory_bank<0> 3.500
memory_bank<1> 3.500
memory_bank<2> 3.500
memory_bank<3> 3.500
memory_bank<4> 3.500
spi_clock 3.500
spi_dataout 3.500


Clock to Setup Times for Clocks

Clock to Setup for clock clock
Source Destination Delay
bus_cnt<0>.Q spi_dataout.D 9.000
bus_cnt<0>.Q tx_register<1>.D 9.000
bus_cnt<0>.Q tx_register<2>.D 9.000
bus_cnt<0>.Q tx_register<3>.D 9.000
bus_cnt<0>.Q tx_register<4>.D 9.000
bus_cnt<0>.Q tx_register<5>.D 9.000
bus_cnt<0>.Q tx_register<6>.D 9.000
bus_cnt<0>.Q tx_register<7>.D 9.000
bus_cnt<1>.Q spi_dataout.D 9.000
bus_cnt<1>.Q tx_register<1>.D 9.000
bus_cnt<1>.Q tx_register<2>.D 9.000
bus_cnt<1>.Q tx_register<3>.D 9.000
bus_cnt<1>.Q tx_register<4>.D 9.000
bus_cnt<1>.Q tx_register<5>.D 9.000
bus_cnt<1>.Q tx_register<6>.D 9.000
bus_cnt<1>.Q tx_register<7>.D 9.000
spi_tx<0>.Q spi_dataout.D 9.000
spi_tx<0>.Q tx_register<1>.D 9.000
spi_tx<0>.Q tx_register<2>.D 9.000
spi_tx<0>.Q tx_register<3>.D 9.000
spi_tx<0>.Q tx_register<4>.D 9.000
spi_tx<0>.Q tx_register<5>.D 9.000
spi_tx<0>.Q tx_register<6>.D 9.000
spi_tx<0>.Q tx_register<7>.D 9.000
spi_tx<1>.Q spi_dataout.D 9.000
spi_tx<1>.Q tx_register<1>.D 9.000
spi_tx<1>.Q tx_register<2>.D 9.000
spi_tx<1>.Q tx_register<3>.D 9.000
spi_tx<1>.Q tx_register<4>.D 9.000
spi_tx<1>.Q tx_register<5>.D 9.000
spi_tx<1>.Q tx_register<6>.D 9.000
spi_tx<1>.Q tx_register<7>.D 9.000
spi_tx<2>.Q spi_dataout.D 9.000
spi_tx<2>.Q tx_register<1>.D 9.000
spi_tx<2>.Q tx_register<2>.D 9.000
spi_tx<2>.Q tx_register<3>.D 9.000
spi_tx<2>.Q tx_register<4>.D 9.000
spi_tx<2>.Q tx_register<5>.D 9.000
spi_tx<2>.Q tx_register<6>.D 9.000
spi_tx<2>.Q tx_register<7>.D 9.000
spi_tx<3>.Q spi_dataout.D 9.000
spi_tx<3>.Q tx_register<1>.D 9.000
spi_tx<3>.Q tx_register<2>.D 9.000
spi_tx<3>.Q tx_register<3>.D 9.000
spi_tx<3>.Q tx_register<4>.D 9.000
spi_tx<3>.Q tx_register<5>.D 9.000
spi_tx<3>.Q tx_register<6>.D 9.000
spi_tx<3>.Q tx_register<7>.D 9.000
OUT1_reg<0>.Q OUT1_reg<0>.D 6.300
OUT1_reg<1>.Q OUT1_reg<1>.D 6.300
bus_cnt<0>.Q OUT1_reg<0>.D 6.300
bus_cnt<0>.Q OUT1_reg<1>.D 6.300
bus_cnt<0>.Q nmi_enable.D 6.300
bus_cnt<0>.Q spi_tx<0>.D 6.300
bus_cnt<1>.Q OUT1_reg<0>.D 6.300
bus_cnt<1>.Q OUT1_reg<1>.D 6.300
bus_cnt<1>.Q nmi_enable.D 6.300
bus_cnt<1>.Q spi_tx<0>.D 6.300
fastpage<0>.Q memory_bank<0>.D 6.300
memory_bank<0>.Q memory_bank<0>.D 6.300
nmi_enable.Q nmi_enable.D 6.300
spi_tx<0>.Q spi_tx<1>.D 6.300
spi_tx<1>.Q spi_tx<1>.D 6.300
bus_cnt<0>.Q bus_cnt<0>.D 5.600
bus_cnt<0>.Q bus_cnt<1>.D 5.600
bus_cnt<0>.Q comms_data.CE 5.600
bus_cnt<0>.Q cts_out.CE 5.600
bus_cnt<0>.Q data_out.CE 5.600
bus_cnt<0>.Q fastpage<0>.D 5.600
bus_cnt<0>.Q fastpage<1>.D 5.600
bus_cnt<0>.Q fastpage<2>.CE 5.600
bus_cnt<0>.Q flashwrite.CE 5.600
bus_cnt<0>.Q memory_bank<0>.CE 5.600
bus_cnt<0>.Q memory_bank<1>.CE 5.600
bus_cnt<0>.Q memory_bank<2>.CE 5.600
bus_cnt<0>.Q memory_bank<3>.CE 5.600
bus_cnt<0>.Q memory_bank<4>.CE 5.600
bus_cnt<0>.Q spi_tx<1>.D 5.600
bus_cnt<0>.Q spi_tx<2>.D 5.600
bus_cnt<0>.Q spi_tx<3>.D 5.600
bus_cnt<0>.Q tx_register<0>.D 5.600
bus_cnt<1>.Q bus_cnt<1>.D 5.600
bus_cnt<1>.Q comms_data.CE 5.600
bus_cnt<1>.Q cts_out.CE 5.600
bus_cnt<1>.Q data_out.CE 5.600
bus_cnt<1>.Q fastpage<0>.D 5.600
bus_cnt<1>.Q fastpage<1>.D 5.600
bus_cnt<1>.Q fastpage<2>.CE 5.600
bus_cnt<1>.Q flashwrite.CE 5.600
bus_cnt<1>.Q memory_bank<0>.CE 5.600
bus_cnt<1>.Q memory_bank<1>.CE 5.600
bus_cnt<1>.Q memory_bank<2>.CE 5.600
bus_cnt<1>.Q memory_bank<3>.CE 5.600
bus_cnt<1>.Q memory_bank<4>.CE 5.600
bus_cnt<1>.Q spi_tx<1>.D 5.600
bus_cnt<1>.Q spi_tx<2>.D 5.600
bus_cnt<1>.Q spi_tx<3>.D 5.600
bus_cnt<1>.Q tx_register<0>.D 5.600
fastpage<0>.Q fastpage<0>.D 5.600
fastpage<1>.Q fastpage<1>.D 5.600
shift<0>.Q rx_register<1>.D 5.600
shift<0>.Q shift<0>.D 5.600
shift<0>.Q shift<1>.D 5.600
shift<1>.Q rx_register<2>.D 5.600
shift<1>.Q shift<1>.D 5.600
shift<1>.Q shift<2>.D 5.600
shift<2>.Q rx_register<3>.D 5.600
shift<2>.Q shift<2>.D 5.600
shift<2>.Q shift<3>.D 5.600
shift<3>.Q rx_register<4>.D 5.600
shift<3>.Q shift<3>.D 5.600
shift<3>.Q shift<4>.D 5.600
shift<4>.Q rx_register<5>.D 5.600
shift<4>.Q shift<4>.D 5.600
shift<4>.Q shift<5>.D 5.600
shift<5>.Q rx_register<6>.D 5.600
shift<5>.Q shift<5>.D 5.600
shift<5>.Q shift<6>.D 5.600
shift<6>.Q rx_register<7>.D 5.600
shift<6>.Q shift<6>.D 5.600
spi_dataout.Q spi_dataout.D 5.600
spi_tx<0>.Q rx_register<0>.CE 5.600
spi_tx<0>.Q rx_register<1>.CE 5.600
spi_tx<0>.Q rx_register<2>.CE 5.600
spi_tx<0>.Q rx_register<3>.CE 5.600
spi_tx<0>.Q rx_register<4>.CE 5.600
spi_tx<0>.Q rx_register<5>.CE 5.600
spi_tx<0>.Q rx_register<6>.CE 5.600
spi_tx<0>.Q rx_register<7>.CE 5.600
spi_tx<0>.Q shift<0>.D 5.600
spi_tx<0>.Q shift<1>.D 5.600
spi_tx<0>.Q shift<2>.D 5.600
spi_tx<0>.Q shift<3>.D 5.600
spi_tx<0>.Q shift<4>.D 5.600
spi_tx<0>.Q shift<5>.D 5.600
spi_tx<0>.Q shift<6>.D 5.600
spi_tx<0>.Q spi_clock.D 5.600
spi_tx<0>.Q spi_tx<0>.D 5.600
spi_tx<0>.Q spi_tx<2>.D 5.600
spi_tx<0>.Q spi_tx<3>.D 5.600
spi_tx<0>.Q tx_register<0>.D 5.600
spi_tx<1>.Q rx_register<0>.CE 5.600
spi_tx<1>.Q rx_register<1>.CE 5.600
spi_tx<1>.Q rx_register<2>.CE 5.600
spi_tx<1>.Q rx_register<3>.CE 5.600
spi_tx<1>.Q rx_register<4>.CE 5.600
spi_tx<1>.Q rx_register<5>.CE 5.600
spi_tx<1>.Q rx_register<6>.CE 5.600
spi_tx<1>.Q rx_register<7>.CE 5.600
spi_tx<1>.Q shift<0>.D 5.600
spi_tx<1>.Q shift<1>.D 5.600
spi_tx<1>.Q shift<2>.D 5.600
spi_tx<1>.Q shift<3>.D 5.600
spi_tx<1>.Q shift<4>.D 5.600
spi_tx<1>.Q shift<5>.D 5.600
spi_tx<1>.Q shift<6>.D 5.600
spi_tx<1>.Q spi_tx<0>.D 5.600
spi_tx<1>.Q spi_tx<2>.D 5.600
spi_tx<1>.Q spi_tx<3>.D 5.600
spi_tx<1>.Q tx_register<0>.D 5.600
spi_tx<2>.Q rx_register<0>.CE 5.600
spi_tx<2>.Q rx_register<1>.CE 5.600
spi_tx<2>.Q rx_register<2>.CE 5.600
spi_tx<2>.Q rx_register<3>.CE 5.600
spi_tx<2>.Q rx_register<4>.CE 5.600
spi_tx<2>.Q rx_register<5>.CE 5.600
spi_tx<2>.Q rx_register<6>.CE 5.600
spi_tx<2>.Q rx_register<7>.CE 5.600
spi_tx<2>.Q shift<0>.D 5.600
spi_tx<2>.Q shift<1>.D 5.600
spi_tx<2>.Q shift<2>.D 5.600
spi_tx<2>.Q shift<3>.D 5.600
spi_tx<2>.Q shift<4>.D 5.600
spi_tx<2>.Q shift<5>.D 5.600
spi_tx<2>.Q shift<6>.D 5.600
spi_tx<2>.Q spi_tx<0>.D 5.600
spi_tx<2>.Q spi_tx<1>.D 5.600
spi_tx<2>.Q spi_tx<2>.D 5.600
spi_tx<2>.Q spi_tx<3>.D 5.600
spi_tx<2>.Q tx_register<0>.D 5.600
spi_tx<3>.Q rx_register<0>.CE 5.600
spi_tx<3>.Q rx_register<1>.CE 5.600
spi_tx<3>.Q rx_register<2>.CE 5.600
spi_tx<3>.Q rx_register<3>.CE 5.600
spi_tx<3>.Q rx_register<4>.CE 5.600
spi_tx<3>.Q rx_register<5>.CE 5.600
spi_tx<3>.Q rx_register<6>.CE 5.600
spi_tx<3>.Q rx_register<7>.CE 5.600
spi_tx<3>.Q shift<0>.D 5.600
spi_tx<3>.Q shift<1>.D 5.600
spi_tx<3>.Q shift<2>.D 5.600
spi_tx<3>.Q shift<3>.D 5.600
spi_tx<3>.Q shift<4>.D 5.600
spi_tx<3>.Q shift<5>.D 5.600
spi_tx<3>.Q shift<6>.D 5.600
spi_tx<3>.Q spi_tx<0>.D 5.600
spi_tx<3>.Q spi_tx<1>.D 5.600
spi_tx<3>.Q spi_tx<2>.D 5.600
spi_tx<3>.Q spi_tx<3>.D 5.600
spi_tx<3>.Q tx_register<0>.D 5.600
tx_register<0>.Q tx_register<0>.D 5.600
tx_register<0>.Q tx_register<1>.D 5.600
tx_register<1>.Q tx_register<1>.D 5.600
tx_register<1>.Q tx_register<2>.D 5.600
tx_register<2>.Q tx_register<2>.D 5.600
tx_register<2>.Q tx_register<3>.D 5.600
tx_register<3>.Q tx_register<3>.D 5.600
tx_register<3>.Q tx_register<4>.D 5.600
tx_register<4>.Q tx_register<4>.D 5.600
tx_register<4>.Q tx_register<5>.D 5.600
tx_register<5>.Q tx_register<5>.D 5.600
tx_register<5>.Q tx_register<6>.D 5.600
tx_register<6>.Q tx_register<6>.D 5.600
tx_register<6>.Q tx_register<7>.D 5.600
tx_register<7>.Q spi_dataout.D 5.600
tx_register<7>.Q tx_register<7>.D 5.600
wait_cnt<0>.Q wait_cnt<0>.D 5.600
wait_cnt<0>.Q wait_cnt<1>.D 5.600
wait_cnt<1>.Q wait_cnt<0>.D 5.600
wait_cnt<1>.Q wait_cnt<1>.D 5.600


Pad to Pad List

Source Pad Destination Pad Delay
address<3> z80_databus<0> 10.400
address<3> z80_databus<1> 10.400
address<3> z80_databus<2> 10.400
address<3> z80_databus<3> 10.400
address<3> z80_databus<4> 10.400
address<3> z80_databus<5> 10.400
address<3> z80_databus<6> 10.400
address<3> z80_databus<7> 10.400
address<4> z80_databus<0> 10.400
address<4> z80_databus<1> 10.400
address<4> z80_databus<2> 10.400
address<4> z80_databus<3> 10.400
address<4> z80_databus<4> 10.400
address<4> z80_databus<5> 10.400
address<4> z80_databus<6> 10.400
address<4> z80_databus<7> 10.400
address<5> z80_databus<0> 10.400
address<5> z80_databus<1> 10.400
address<5> z80_databus<2> 10.400
address<5> z80_databus<3> 10.400
address<5> z80_databus<4> 10.400
address<5> z80_databus<5> 10.400
address<5> z80_databus<6> 10.400
address<5> z80_databus<7> 10.400
address<6> z80_databus<0> 10.400
address<6> z80_databus<1> 10.400
address<6> z80_databus<2> 10.400
address<6> z80_databus<3> 10.400
address<6> z80_databus<4> 10.400
address<6> z80_databus<5> 10.400
address<6> z80_databus<6> 10.400
address<6> z80_databus<7> 10.400
address<7> z80_databus<0> 10.400
address<7> z80_databus<1> 10.400
address<7> z80_databus<2> 10.400
address<7> z80_databus<3> 10.400
address<7> z80_databus<4> 10.400
address<7> z80_databus<5> 10.400
address<7> z80_databus<6> 10.400
address<7> z80_databus<7> 10.400
if1_enable z80_databus<0> 10.400
if1_enable z80_databus<1> 10.400
if1_enable z80_databus<2> 10.400
if1_enable z80_databus<3> 10.400
if1_enable z80_databus<4> 10.400
if1_enable z80_databus<5> 10.400
if1_enable z80_databus<6> 10.400
if1_enable z80_databus<7> 10.400
kempston_enable z80_databus<0> 10.400
kempston_enable z80_databus<1> 10.400
kempston_enable z80_databus<2> 10.400
kempston_enable z80_databus<3> 10.400
kempston_enable z80_databus<4> 10.400
kempston_enable z80_databus<5> 10.400
kempston_enable z80_databus<6> 10.400
kempston_enable z80_databus<7> 10.400
address<0> z80_databus<0> 7.000
address<0> z80_databus<1> 7.000
address<0> z80_databus<2> 7.000
address<0> z80_databus<3> 7.000
address<0> z80_databus<4> 7.000
address<0> z80_databus<5> 7.000
address<0> z80_databus<6> 7.000
address<0> z80_databus<7> 7.000
address<1> z80_databus<0> 7.000
address<1> z80_databus<1> 7.000
address<1> z80_databus<2> 7.000
address<1> z80_databus<3> 7.000
address<1> z80_databus<4> 7.000
address<1> z80_databus<5> 7.000
address<1> z80_databus<6> 7.000
address<1> z80_databus<7> 7.000
address<2> z80_databus<0> 7.000
address<2> z80_databus<1> 7.000
address<2> z80_databus<2> 7.000
address<2> z80_databus<3> 7.000
address<2> z80_databus<4> 7.000
address<2> z80_databus<5> 7.000
address<2> z80_databus<6> 7.000
address<2> z80_databus<7> 7.000
rs_232in z80_nmi 7.000
z80_iorq z80_databus<0> 7.000
z80_iorq z80_databus<1> 7.000
z80_iorq z80_databus<2> 7.000
z80_iorq z80_databus<3> 7.000
z80_iorq z80_databus<4> 7.000
z80_iorq z80_databus<5> 7.000
z80_iorq z80_databus<6> 7.000
z80_iorq z80_databus<7> 7.000
z80_mreq memory_bank<3> 7.000
z80_mreq memory_bank<4> 7.000
z80_rd z80_databus<0> 7.000
z80_rd z80_databus<1> 7.000
z80_rd z80_databus<2> 7.000
z80_rd z80_databus<3> 7.000
z80_rd z80_databus<4> 7.000
z80_rd z80_databus<5> 7.000
z80_rd z80_databus<6> 7.000
z80_rd z80_databus<7> 7.000
kempston<0> z80_databus<0> 6.000
memory_bank<4> z80_databus<3> 6.000
dtr_in z80_databus<3> 5.700
hi_address<0> rom_cs 5.700
hi_address<1> rom_cs 5.700
kempston<1> z80_databus<1> 5.700
net_in z80_databus<0> 5.700
reset rom_cs 5.700
rs_232in z80_databus<7> 5.700
z80_mreq rom_cs 5.700
z80_rd rom_cs 5.700
hi_address<0> ram_cs 5.000
hi_address<1> ram_cs 5.000
kempston<2> z80_databus<2> 5.000
memory_bank<3> z80_databus<4> 5.000
reset ram_cs 5.000
z80_mreq ram_cs 5.000
z80_rd edge_romcs 5.000
z80_rd ram_cs 5.000
z80_wr ram_cs 5.000
z80_wr rom_cs 5.000


Number of paths analyzed: 799
Number of Timing errors: 799
Analysis Completed: Sun Jan 11 22:51:24 2009