8520 Complex Interface Adapters 
===============================

Amiga contains two CIA chips: CIAA and CIAB


CIAA Address Map
----------------

---------------------------------------------------------------------------
 Byte    Register                  Data bits
Address    Name            7     6     5     4     3     2     1    0
---------------------------------------------------------------------------
BFE001    pra     Port A  /FIR1 /FIR0  /RDY /TK0  /WPRO /CHNG /LED  OVL
BFE101    prb     Port B (parallel port)
BFE201    ddra    Direction for port A (BFE001) 0=input 1=output (set to 0x03)
BFE301    ddrb    Direction for port B (BFE101) 0-input 1=output (can be in or out)
BFE401    talo    CIAA timer A low byte (0.715909 MHz NTSC; 0.709379 MHz PAL)
BFE501    tahi    CIAA timer A high byte
BFE601    tblo    CIAA timer B low byte (0.715909 MHz NTSC; 0.709379 MHz PAL)
BFE701    tbhi    CIAA timer B high byte
BFE801    todlo   vertical sync (50 or 60 Hz) event counter bits 7-0 (VSync or line tick)
BFE901    todmid  vertical sync (50 or 60 Hz) event counter bits 15-8
BFEA01    todhi   vertical sync (50 or 60 Hz) event counter bits 23-16
BFEB01            unused
BFEC01    sdr     CIAA serial data register (connected to keyboard)
BFED01    icr     CIAA interrupt control register
                  Read:   IR        0    0   FLG  SP   ALRM TB  TA
                  Write:  Set/Clear x    x   FLG  SP   ALRM TB  TA
BFEE01    cra     CIAA control register A
BFEF01    crb     CIAA control register B

TA = Timer A
TB = Timer B
SP = Serial Port
FLG = Flag (TODO: What is this?)

Note:  CIAA can generate interrupt INT2.


CIAB Address Map
----------------

---------------------------------------------------------------------------
 Byte     Register                   Data bits
Address     Name     7     6     5     4     3     2     1     0
---------------------------------------------------------------------------
BFD000    pra     /DTR  /RTS  /CD   /CTS  /DSR   SEL   POUT  BUSY
BFD100    prb     /MTR  /SEL3 /SEL2 /SEL1 /SEL0 /SIDE  DIR  /STEP
BFD200    ddra    Direction for Port A (BFD000);1 = output (set to 0xFF)
BFD300    ddrb    Direction for Port B (BFD100);1 = output (set to 0xFF)
BFD400    talo    CIAB timer A low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
BFD500    tahi    CIAB timer A high byte
BFD600    tblo    CIAB timer B low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
BFD700    tbhi    CIAB timer B high byte
BFD800    todlo   Horizontal sync event counter bits 7-0
BFD900    todmid  Horizontal sync event counter bits 15-8
BFDA00    todhi   Horizontal sync event counter bits 23-16
BFDB00            unused
BFDC00    sdr     CIAB serial data register (unused)
BFDD00    icr     CIAB interrupt control register
BFDE00    cra     CIAB Control register A
BFDF00    crb     CIAB Control register B

Note:  CIAB can generate INT6.

All unused register bits are unaffected by a write and forced to 0 on a read.

---------------------------------------------------------------------------

Calculating timings
===================

There are two control registers in the 8520, CRA and CRB. CRA is associated with  
Timer A  and CRB is associated with Timer B.

Control Register A
------------------

CIAA_CRA = $BFEE01
CIAB_CRA = $BFDE00

  BIT  NAME     FUNCTION
  ---  ----     --------
   0   START    1 = start Timer A, 0 = stop Timer A.
                    This bit is automatically reset (= 0) when
                    underflow occurs during one-shot mode.
   1   PBON     1 = Timer A output on PB6, 0 = is normal operation.
   2   OUTMODE  1 = toggle, 0 = pulse.
   3   RUNMODE  1 = one-shot mode, 0 = continuous mode.
   4   LOAD     1 = force load (this is a strobe input, there is no
                    data storage;  bit 4 will always read back a zero
                    and writing a 0 has no effect.)
   5   INMODE   1 = Timer A counts positive CNT transitions,
                0 = Timer A counts 02 pulses.
   6   SPMODE   1 = Serial port=output (CNT is the source of the shift
                    clock)
                0 = Serial port=input  (external shift clock is
                    required)
   7   UNUSED


REG# NAME UNUSED  SPMODE  INMODE  LOAD   RUNMODE  OUTMODE   PBON    START
---- ---- ------  ------  ------  ----   -------  -------   ----    -----
 E   CRA  unused  0=input  0=02  1=force  0=cont. 0=pulse  0=PB6OFF 0=stop
          unused  1=output 1=CNT   load   1=one-  1=toggle 1=PB6ON  1=start
                                 (strobe)   shot

Control Register B
------------------

CIAA_CRB = $BFEF01
CIAB_CRB = $BFDF00

  BIT  NAME     FUNCTION
  ---  ----     --------
   0   START    1 = start Timer B, 0 = stop Timer B.
                    This bit is automatically reset (= 0) when
                    underflow occurs during one-shot mode.
   1   PBON     1 = Timer B output on PB7, 0 = PB7 is normal
                    operation.
   2   OUTMODE  1 = toggle, 0 = pulse.
   3   RUNMODE  1 = one-shot mode, 0 = continuous mode.
   4   LOAD     1 = force load (this is a strobe input, there is no
                    data storage;  bit 4 will always read back a
                    zero and writing a 0 has no effect.)
  6,5  INMODE   Bits CRB6 and CRB5 select one of four possible
                input modes for Timer B, as follows:

                CRB6  CRB5   Mode Selected
                ----  ----   ---------------------------------------
                 0     0     Timer B counts 02 pulses
                 0     1     Timer B counts positive CNT transitions
                 1     0     Timer B counts Timer A underflow pulses
                 1     1     Timer B counts Timer A underflow pulses
                               while CNT pin is held high.

   7   ALARM     1 = writing to TOD registers sets Alarm
                 0 = writing to TOD registers sets TOD clock.
                     Reading TOD registers always reads TOD clock,
                     regardless of the state of the Alarm bit.

Bitmap of Register CRB

REG# NAME ALARM    INMODE     LOAD      RUNMODE  OUTMODE  PBON    START
---- ---- -----    ------     ----      -------  -------  ----    -----
 F   CRB  0=TOD    00=02      1=force   0=cont.  0=pulse  0=PB7OFF 0=stop
          1=Alarm  01=CNT       load    1=one-   1=toggle 1=PB7ON  1=start
                   10=Timer A  (strobe)   shot
                   11=CNT+
                     Timer A

                   |<---------------  Timer B  Variables ------------>|


In continuous mode, the timer will count down from the latched value to zero, generate 
an interrupt, reload the latched value, and repeat the procedure continuously.

In one-shot mode, the timer will count down from the latched value to zero, generate an
interrupt, reload the latched value, then stop. In one-shot mode, a write to timer-high
register will transfer the timer latch to the counter and initiate counting regardless
of the start bit.

---------------------------------------------------------------------------------------

Timing Example
--------------

See Hardware Reference Manual

http://amigadev.elowar.com/read/ADCD_2.1/Hardware_Manual_guide/node02E1.html

The base Amiga crystal frequencies are:
    NTSC    28.63636  MHz
    PAL     28.37516  MHz

This "Color Clock" frequency is divided by 4 to get the System (CPU) Clock frequency:
    NTSC    7.15909  MHz
    PAL     7.09379  MHz

The two 16 bit timers on the 8520 chips each count down at 1/10 the CPU
clock:
    NTSC    0.715909 MHz
    PAL     0.709379 MHz

Taking the reciprocal gives the time per cycle:
    NTSC    1.3968255 microseconds/cycle
    PAL     1.4096836 microseconds/cycle

Knowing the time per cycle allows the CIA timer register value for a desired time to be calculated.

Example 1: Calculate the timer register value to wait for 1/100 second on NTSC

    1/100 = 10000 microseconds.
    10000 microseconds / 1.3968255 microseconds/cycle = 7159 cycles

Example 2: Calculate the timer register value to wait for 3 milliseconds on PAL

    3 miliseconds = 3000 microseconds
    3000 microseconds / 1.4096836 microseconds/cycle = 2128 cycles

Example 3: The hardware MFM loader code in Chase HQ uses a timer value of $8bd4. What timer value 
does this correspond to on a PAL machine?

    $8bd4 = 35796 cycles
    35796 cycles * 1.4096836 microseconds/cycle = 50461 microseconds = 50.461 milliseconds

------------------------------------------------------------------------------------------------

Stepping Disk Drive Heads
-------------------------

CIAB PRB
                                       bit
Address   Name     7     6     5     4     3     2     1     0
BFD100    prb     /MTR  /SEL3 /SEL2 /SEL1 /SEL0 /SIDE  DIR  /STEP

DIR AKA DSKDIREC: 
    1 = step outwards towards track 0 at outside of disk
    0 = step inwards towards centre spindle of disk, away from track 0

------------------------------------------------------------------------------------------------

Turning the drive motor on and off
----------------------------------

CIAB PRB bit 7 /MTR (active low)

After turning on the motor, software must further wait for one half second (500ms) or for the 
DSKRDY* line to go low.

------------------------------------------------------------------------------------------------

See Hardware Reference Manual Appendix F for more info.

