La derni\u00e8re version b\u00e9ta publique de l’excellent WinUAE, l’\u00e9mulateur Commodore Amiga.<\/p>\n
<\/p>\n
– 68030 prefetch\/ce mode now also uses improved prefetch pipeline emulation.<\/em> Rochard RH800C with v2 boot ROM:<\/em> M-Tec E-Matrix 530:<\/em> <\/p>\n Source: Forum des versions Betas<\/a>.<\/p>\n T\u00e9l\u00e9charger WinUAE (Public Beta) v3.2.0 Beta 7 (3,2 Mo)<\/a><\/p>\n
\n – b4 prefetch RTS (and others) special case does not exist, my original test must have been broken.<\/em>
\n – GUI won’t anymore allow multiple sound or network cards enabled at the same. (It has never been supported configuration)<\/em>
\n – Cirrus Logic out of bounds VRAM access check improved.<\/em>
\n – Picasso IV ROM loader update didn’t support all old ROM paths (b6)<\/em>
\n – SCSI Unit Attention (bus reset\/media change) status handling should be now exactly as described in SCSI spec. (Roctec Rochard v2 boot ROM)<\/em>
\n – A1060 Diagnostics and 8087 jumper was inverted.<\/em>
\n – Continuing WD SCSI transfer with another Select and Transfer when previous SaT had already transferred all buffered data: new SaT restarted from beginning. (A590\/A2091 omniscsi.device + cdfs)<\/em>
\n – Config file loaded with non-existing *_rom_file_id: rom key file (\u00ab\u00a0rom\u00a0\u00bb with ID=0) was selected.<\/em>
\n – M-Tec E-Matrix 530 accelerator board added (Thanks to Jozsef Vamosi)<\/em><\/p>\n
\n – Supports both SCSI and IDE. v1 is IDE only.<\/em>
\n – Has crazy \u00ab\u00a0Is drive ready?\u00a0\u00bb polling routine, driver executes 300 (!) TEST UNIT READY commands in CPU loop per LUN (timer.device exists for a reason..), with single SCSI drive, driver executes total 6*300=1800 TUR commands during drive detection! (I recommend not to enable scsi logging..)<\/em>
\n – ROM not yet added.<\/em><\/p>\n
\n – ROM image is software dumped (chip is not socketed), ROM layout (single chip contains two logical autoconfig boot ROMs) may not match real ROM dump.<\/em>
\n – 53C94 based SCSI. Fake DMA, 2*long word wide data port. Whole transfer loop runs in level 2 interrupt routine..<\/em>
\n – Boot ROM requires KS2.0+ only because it calls CacheControl() without checking ROM version.<\/em><\/p>\n